Jacob SAVIR


Effect of BIST Pretest on IC Defect Level
Yoshiyuki NAKAMURA Jacob SAVIR Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/10/01
Vol. E89-D  No. 10  pp. 2626-2636
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
BISTfault coveragedefect level
 Summary | Full Text:PDF(1.2MB)

Power-Constrained Test Synthesis and Scheduling Algorithms for Non-Scan BIST-able RTL Data Paths
Zhiqiang YOU Ken'ichi YAMAGUCHI Michiko INOUE Jacob SAVIR Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/08/01
Vol. E88-D  No. 8  pp. 1940-1947
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
design for testabilityRTL data pathbuilt-in self-testlow power testingtest scheduling
 Summary | Full Text:PDF(447.5KB)

Defect Level vs. Yield and Fault Coverage in the Presence of an Unreliable BIST
Yoshiyuki NAKAMURA Jacob SAVIR Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/06/01
Vol. E88-D  No. 6  pp. 1210-1216
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
BISTfault coveragedefect level
 Summary | Full Text:PDF(629.9KB)

Analog Circuit Test Using Transfer Function Coefficient Estimates
Zhen GUO Jacob SAVIR 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/03/01
Vol. E87-D  No. 3  pp. 642-646
Type of Manuscript:  Special Section LETTER (Special Section on Test and Verification of VLSI)
Category: 
Keyword: 
fault detectionparametric faultsMonte-Carlo simulationsystem identification
 Summary | Full Text:PDF(116.7KB)

RAM BIST
Jacob SAVIR 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/01/01
Vol. E84-C  No. 1  pp. 102-107
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
memory teststuck-at faultcoupled-cell faultspattern-sensitive faultstest lengthconfidence levelMarkov chain
 Summary | Full Text:PDF(204.8KB)