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Improving Dictionary-Based Code Compression in VLIW Architectures Sang-Joon NAM
In-Cheol PARK
Chong-Min KYUNG
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Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/20
Vol. E82-A
No. 11
pp. 2318-2324
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Keyword: code compression,
VLIW architecture,
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(1.7MB)
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SEWD: A Cache Architecture to Speed up the Misaligned Instruction Prefetch Joon-Seo YIM
In-Cheol PARK
Chong-Min KYUNG
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Publication: IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/07/20
Vol. E80-D
No. 7
pp. 742-745
Type of Manuscript: LETTER
Category: Computer Hardware and Design Keyword: cache,
microprocessor,
pipeline,
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(304.6KB)
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Hardware Accelerator for Outline Font Generation Gyu-Cheol HWANG
In-Cheol PARK
Yun-Tae LEE
Tae-Hyung LEE
Jong-Hong BAE
Chong-Min KYUNG
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Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1991/10/20
Vol. E74-A
No. 10
pp. 3078-3082
Type of Manuscript: Special Section PAPER (Special Issue on JTC-CSCC '90)
Category: VLSI Design Technology Keyword:
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(472.1KB)
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