Hyungcheol SHIN


L-Shaped Tunneling Field-Effect Transistors for Complementary Logic Applications
Sang Wan KIM  Woo Young CHOI  Min-Chul SUN  Hyun Woo KIM  Jong-Ho LEE  Hyungcheol SHIN  Byung-Gook PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/05/01
Vol. E96-C  No. 5  pp. 634-638
Type of Manuscript: Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: 
Keyword: 
L-shaped TFETssubthreshold swingsteep slopecomplementary logic function
  Summary |  Full Text:PDF (2.8MB)

Simulation Study on Dependence of Channel Potential Self-Boosting on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
Seongjae CHO  Jung Hoon LEE  Yoon KIM  Jang-Gn YUN  Hyungcheol SHIN  Byung-Gook PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/05/01
Vol. E93-C  No. 5  pp. 596-601
Type of Manuscript: Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: Flash/Advanced Memory
Keyword: 
NANDflash memoryprogram inhibitionself-boostingFinFETdevice simulation
  Summary |  Full Text:PDF (1.2MB)

Design Consideration for Vertical Nonvolatile Memory Device Regarding Gate-Induced Barrier Lowering (GIBL)
Seongjae CHO  Jung Hoon LEE  Gil Sung LEE  Jong Duk LEE  Hyungcheol SHIN  Byung-Gook PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/05/01
Vol. E92-C  No. 5  pp. 620-626
Type of Manuscript: Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: 
Keyword: 
3-D nonvolatile memoryNAND flash memory arraysaturation currentchannel potential barriergate-induced barrier lowering (GIBL)
  Summary |  Full Text:PDF (748.5KB)

Application of the Compact Channel Thermal Noise Model of Short Channel MOSFETs to CMOS RFIC Design
Jongwook JEON  Ickhyun SONG  Jong Duk LEE  Byung-Gook PARK  Hyungcheol SHIN 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/05/01
Vol. E92-C  No. 5  pp. 627-634
Type of Manuscript: Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: 
Keyword: 
CMOSchannel thermal noiseradio frequency integrated circuit (RFIC)low noise amplifier (LNA)noise figure
  Summary |  Full Text:PDF (1.9MB)

3-Dimensional Terraced NAND (3D TNAND) Flash Memory-Stacked Version of Folded NAND Array
Yoon KIM  Seongjae CHO  Gil Sung LEE  Il Han PARK  Jong Duk LEE  Hyungcheol SHIN  Byung-Gook PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/05/01
Vol. E92-C  No. 5  pp. 653-658
Type of Manuscript: Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: 
Keyword: 
NANDflash memorystacked NANDvertical channel
  Summary |  Full Text:PDF (716.6KB)

Simulation of Retention Characteristics in Double-Gate Structure Multi-Bit SONOS Flash Memory
Doo-Hyun KIM  Il Han PARK  Seongjae CHO  Jong Duk LEE  Hyungcheol SHIN  Byung-Gook PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/05/01
Vol. E92-C  No. 5  pp. 659-663
Type of Manuscript: Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: 
Keyword: 
SONOSflash memorynitride-based charge trap memoryretentionmulti-bitdouble gate
  Summary |  Full Text:PDF (621.2KB)

Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI)
Seongjae CHO  Il Han PARK  Jung Hoon LEE  Jang-Gn YUN  Doo-Hyun KIM  Jong Duk LEE  Hyungcheol SHIN  Byung-Gook PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/05/01
Vol. E91-C  No. 5  pp. 731-735
Type of Manuscript: Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: 
Keyword: 
memory arrayelectrical interference3-D memory deviceread operationPCI (paired cell interference)
  Summary |  Full Text:PDF (809.4KB)

FN Stress Induced Degradation on Random Telegraph Signal Noise in Deep Submicron NMOSFETs
Hochul LEE  Youngchang YOON  Ickhyun SONG  Hyungcheol SHIN 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/05/01
Vol. E91-C  No. 5  pp. 776-779
Type of Manuscript: Special Section LETTER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: 
Keyword: 
random telegraph signal noiseFN stressflash memoryMOSFET
  Summary |  Full Text:PDF (661.2KB)

Analyses on Current Characteristics of 3-D MOSFET Determined by Junction Doping Profiles for Nonvolatile Memory Devices
Seongjae CHO  Jang-Gn YUN  Il Han PARK  Jung Hoon LEE  Jong Pil KIM  Jong-Duk LEE  Hyungcheol SHIN  Byung-Gook PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/05/01
Vol. E90-C  No. 5  pp. 988-993
Type of Manuscript: Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: Novel MOSFET Structures
Keyword: 
3-D devicesvertical ion implantationdoping profileconcentration peakdoping gradient
  Summary |  Full Text:PDF (986.6KB)

Accurate Extraction of the Trap Depth from RTS Noise Data by Including Poly Depletion Effect and Surface Potential Variation in MOSFETs
Hochul LEE  Youngchang YOON  Seongjae CHO  Hyungcheol SHIN 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/05/01
Vol. E90-C  No. 5  pp. 968-972
Type of Manuscript: Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: Ultra-Thin Gate Insulators
Keyword: 
trap depthRTNtime constantspoly gate depletion effectsurface potential variation
  Summary |  Full Text:PDF (801KB)

Characteristics of MOSFET with Non-overlapped Source-Drain to Gate
Hyunjin LEE  Sung-il CHANG  Jongho LEE  Hyungcheol SHIN 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/05/01
Vol. E85-C  No. 5  pp. 1079-1085
Type of Manuscript: Special Section PAPER (Special Issue on Advanced Sub-0.1 µm CMOS Devices)
Category: 
Keyword: 
non-overlap50 nm MOSFETSCEextended source/drain
  Summary |  Full Text:PDF (1.2MB)