Hsueh-Chih YANG

A Parallel-In Folding Technique for High-Order FIR Filter Implementation
Lan-Rong DUNG  Hsueh-Chih YANG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12  pp. 3659-3665
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Architecture
Keyword: 
FIR,  VLSI hardware,  digital filters, 
  Summary |  Full Text:PDF (493.3KB)
On Multiple-Voltage High-Level Synthesis Using Algorithmic Transformations
Lan-Rong DUNG  Hsueh-Chih YANG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12  pp. 3100-3108
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
multiple voltage scheduling,  low-power circuit,  loop shrinking,  retiming,  unfolding,  high-level synthesis, 
  Summary |  Full Text:PDF (833.4KB)