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Hong-June PARK

An Analysis and Design Methodology of Resistor-Based Phase Error Averaging for Multiphase Generation Young-Sang KIM Yunjae SUH Hong-June PARK Jae-Yoon SIM
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2010/12/01 Vol. E93-C No. 12 pp. 1662-1669 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: multiphase clock generation, error averaging, ring oscillator,
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A Digital Differential Transmitter with Pseudo-LVDS Output Driver and Digital Mismatch Calibration Jun-Hyun BAE Sang-Hune PARK Jae-Yoon SIM Hong-June PARK
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2010/01/01 Vol. E93-C No. 1 pp. 132-135 Type of Manuscript: BRIEF PAPER Category: Electronic Circuits Keyword: differential, digital transmitter, termination,
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A Distortion-Free General Purpose LVDS Driver Seung-Jin PARK Young Hun SEO Hong-June PARK Jae-Yoon SIM
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2009/02/01 Vol. E92-C No. 2 pp. 278-280 Type of Manuscript: LETTER Category: Electronic Circuits Keyword: LVDS, output driver, level-shifter, simultaneous switching noise,
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Deadzone-Minimized Systematic Offset-Free Phase Detectors Young-Sang KIM Yunjae SUH Hong-June PARK Jae-Yoon SIM
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/09/01 Vol. E91-C No. 9 pp. 1525-1528 Type of Manuscript: LETTER Category: Integrated Electronics Keyword: phase detector, phase offset, deadzone, multiphase generation, delay-locked loop, phase-locked loop,
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An 8.8-GS/s 6-bit CMOS Time-Interleaved Flash Analog-to-Digital Converter with Multi-Phase Clock Generator Young-Chan JANG Jun-Hyun BAE Sang-Hune PARK Jae-Yoon SIM Hong-June PARK
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/06/01 Vol. E90-C No. 6 pp. 1156-1164 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: flash ADC, time-interleaving, phase-locked-loop, digital phase adjuster, digital duty cycle corrector,
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An All-Digital CMOS Duty Cycle Correction Circuit with a Duty-Cycle Correction Range of 15-to-85% for Multi-Phase Applications Jang-Jin NAM Hong-June PARK
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2005/04/01 Vol. E88-C No. 4 pp. 773-777 Type of Manuscript: LETTER Category: Electronic Circuits Keyword: duty cycle correction, all-digital, multi-phase clock, PLL/DLL,
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A Decision Feedback Equalizing Receiver for the SSTL SDRAM Interface with Clock-Data Skew Compensation Young-Soo SOHN Seung-Jun BAE Hong-June PARK Soo-In CHO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/05/01 Vol. E87-C No. 5 pp. 809-817 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: SDRAM I/O interface, receiver equalization, SSTL, decision feedback equalization, clock-data skew compensation, X2 over-sampling phase detector,
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An 8-GS/s 4-Bit 340 mW CMOS Time Interleaved Flash Analog-to-Digital Converter Young-Chan JANG Sang-Hune PARK Seung-Chan HEO Hong-June PARK
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/02/01 Vol. E87-A No. 2 pp. 350-356 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: analog-to-digital converter, time interleaved flash converter, resistor averaging, distributed track-and-hold, phase locked loop,
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CMOS Sense-Amplifier Type Flip-Flop Having Improved Setup/Hold Margin Seong-Ik CHO Jin-Seok HEO Hong-June PARK Mu-Hun PARK Young-Hee KIM
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2003/12/01 Vol. E86-C No. 12 pp. 2508-2510 Type of Manuscript: LETTER Category: Integrated Electronics Keyword: flip-flop, sense-amplifier, receiver,
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An 8-Bit 200 MS/s CMOS Folding/Interpolating Analog-to-Digital Converter Seung-Chan HEO Young-Chan JANG Sang-Hune PARK Hong-June PARK
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2003/04/01 Vol. E86-C No. 4 pp. 676-681 Type of Manuscript: LETTER Category: Electronic Circuits Keyword: analog-to-digital converter (ADC), resistor averaging, folding, interpolating, differential logic,
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A Compact Radix-64 54 54 CMOS Redundant Binary Parallel Multiplier Sang-Hoon LEE Seung-Jun BAE Hong-June PARK
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2002/06/01 Vol. E85-C No. 6 pp. 1342-1350 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: parallel multiplier, redundant binary, radix-64, CMOS circuit, digital circuit,
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A Temperature- and Supply-Insensitive Fully On-Chip 1 Gb/s CMOS Open-Drain Output Driver for High-Bandwidth DRAMs Young-Hee KIM Jong-Doo JOO Jae-Kyung WEE Jin-Yong CHUNG Young-Soo SOHN Hong-June PARK
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2002/01/01 Vol. E85-C No. 1 pp. 204-211 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: supply-insensitive, voltage-insensitive, open-drain, output driver, high-bandwidth DRAMs,
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An Analytic Time Jitter Equation of NRZ Signals in Uniformly Loaded PCB Transmission Lines Won-Ki PARK Young-Soo SOHN Jin-Seok PARK Hong-June PARK Soo-In CHO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2001/09/01 Vol. E84-C No. 9 pp. 1264-1266 Type of Manuscript: LETTER Category: Electronic Circuits Keyword: time jitter, loaded transmission line, digital signal, inter-symbol interference (ISI),
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Two-Phase Boosted Voltage Generator for Low-Voltage Giga-Bit DRAMs Young-Hee KIM Jong-Ki NAM Sang-Hoon LEE Hong-June PARK Joo-Sun CHOI Choon-Sung PARK Seung-Han AHN Jin-Yong CHUNG
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2000/02/20 Vol. E83-C No. 2 pp. 266-269 Type of Manuscript: LETTER Category: Storage Technology Keyword: boosted voltage generator, low voltage, giga-bit DRAMs, charge pump,
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Fully On-Chip Current Controlled Open-Drain Output Driver for High-Bandwidth DRAMs Young-Hee KIM Jong-Ki NAM Young-Soo SOHN Hong-June PARK Ki-Bong KU Jae-Kyung WEE Joo-Sun CHOI Choon-Sung PARK
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/11/20 Vol. E82-C No. 11 pp. 2101-2104 Type of Manuscript: LETTER Category: Integrated Electronics Keyword: current controlled, supply-insensitive, voltage-insensitive, open-drain, output driver, high-bandwidth DRAMs,
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A Low-Power Half-Swing Clocking Scheme for Flip-Flop with Complementary Gate and Source Drive Jin-Cheon KIM Sang-Hoon LEE Hong-June PARK
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/09/20 Vol. E82-C No. 9 pp. 1777-1779 Type of Manuscript: LETTER Category: Integrated Electronics Keyword: CMOS flip-flop, low power, half-swing clocking, complementary drive,
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Single-Chip Implementation of a 32-bit Motor-Drive-Specific Microcontroller with Floating-Point Unit Jin-Cheon KIM Sang-Hoon LEE Joo-Hyun LEE Do-Young LEE Won-Chang JUNG Hong-June PARK Im-Soo MOK Hyung-Gyun KIM Ga-Woo PARK
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/09/20 Vol. E82-C No. 9 pp. 1699-1706 Type of Manuscript: Special Section PAPER (Special Issue on Integrated Electronics and New System Paradigms) Category: Processors Keyword: motor drive, 32-bit microcontroller, single-chip, floating-point unit, RISC, CMOS VLSI,
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Adaptive Biasing Folded Cascode CMOS OP Amp with Continuous-Time Push-Pull CMFB Scheme Jae-Yoon SIM Cheol-Hee LEE Won-Chang JEONG Hong-June PARK
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/09/20 Vol. E80-C No. 9 pp. 1203-1210 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: CMOS OP amp, common mode feedback (CMFB), slew rate, adaptive bias, push-pull,
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A Temperature-Insensitive Current Controlled CMOS Output Driver Cheol-Hee LEE Jae-Yoon SIM Hong-June PARK
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/12/20 Vol. E79-C No. 12 pp. 1726-1732 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: CMOS output driver, temperature-insensitive, current reference, CMOS square root, current controlled,
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