Hisako SATO


Efficient Application of Hot-Carrier Reliability Simulation to Delay Library Screening for Reliability of Logic Designs
Hisako SATO Mariko OHTSUKA Kazuya MAKABE Yuichi KONDO Kazumasa YANAGISAWA Peter M. LEE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/05/01
Vol. E86-C  No. 5  pp. 842-849
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
hot-carriercircuit reliabilitysimulationdelay librarylogic design
 Summary | Full Text:PDF(1.1MB)

Delay Library Generation with High Efficiency and Accuracy on the Basis of RSM
Hisako SATO Yuko ITO Hisaaki KUNITOMO Hiroyuki BABA Satoru ISOMURA Hiroo MASUDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2000/08/25
Vol. E83-C  No. 8  pp. 1295-1302
Type of Manuscript:  Special Section PAPER (Special Issue on 1999 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'99))
Category: Simulation Methodology and Environment
Keyword: 
delay libraryRSMcircuit simulation
 Summary | Full Text:PDF(1.2MB)

A New Hierarchical RSM for TCAD-Based Device Design in 0.4µm CMOS Development
Hisako SATO Katsumi TSUNENO Kimiko AOYAMA Takahide NAKAMURA Hisaaki KUNITOMO Hiroo MASUDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/02/25
Vol. E79-C  No. 2  pp. 226-233
Type of Manuscript:  Special Section PAPER (Special Issue on Microelectronic Test Structures)
Category: Statistical Analysis
Keyword: 
TCADRSMCMOS design
 Summary | Full Text:PDF(742.5KB)

Modeling and Simulation on Degradation of Submicron NMOSFET Current Drive due to Velocity-Saturation Effects
Katsumi TSUNENO Hisako SATO Hiroo MASUDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/02/25
Vol. E77-C  No. 2  pp. 161-165
Type of Manuscript:  Special Section PAPER (Special Issue on 1993 VLSI Process and Device Modeling Workshop (VPAD 93))
Category: Device Simulation
Keyword: 
degradation of drain currentvelocity-saturationIdsolateral electric field
 Summary | Full Text:PDF(411.7KB)

Evaluation of Two-Dimensional Transient Enhanced Diffusion of Phosphorus during Shallow Junction Formation
Hisako SATO Katsumi TSUNENO Hiroo MASUDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/02/25
Vol. E77-C  No. 2  pp. 106-111
Type of Manuscript:  Special Section PAPER (Special Issue on 1993 VLSI Process and Device Modeling Workshop (VPAD 93))
Category: Process Simulation
Keyword: 
transient enhanced diffusiontwo-dimensionphosphorussiliconshallow junctionfurnace annealing
 Summary | Full Text:PDF(517.8KB)