Hiroyuki YOTSUYANAGI


A Design for Testability of Open Defects at Interconnects in 3D Stacked ICs
Fara ASHIKIN Masaki HASHIZUME Hiroyuki YOTSUYANAGI Shyue-Kung LU Zvi ROTH 
Publication:   
Publication Date: 2018/08/01
Vol. E101-D  No. 8  pp. 2053-2063
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
3D stacked ICopen defectsdesign-for-testabilitythrough-silicon viaelectrical interconnect test
 Summary | Full Text:PDF(934.9KB)

Discrimination of a Resistive Open Using Anomaly Detection of Delay Variation Induced by Transitions on Adjacent Lines
Hiroyuki YOTSUYANAGI Kotaro ISE Masaki HASHIZUME Yoshinobu HIGAMI Hiroshi TAKAHASHI 
Publication:   
Publication Date: 2017/12/01
Vol. E100-A  No. 12  pp. 2842-2850
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
resistive opensmall delay faultadjacent linedelay variationanomaly detection
 Summary | Full Text:PDF(1.2MB)

A Built-in Test Circuit for Electrical Interconnect Testing of Open Defects in Assembled PCBs
Widiant Masaki HASHIZUME Shohei SUENAGA Hiroyuki YOTSUYANAGI Akira ONO Shyue-Kung LU Zvi ROTH 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/11/01
Vol. E99-D  No. 11  pp. 2723-2733
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
electrical testbuilt-in test circuitopen defectinterconnect testdesign for testability
 Summary | Full Text:PDF(2.5MB)

SAT-Based Test Generation for Open Faults Using Fault Excitation Caused by Effect of Adjacent Lines
Jun YAMASHITA Hiroyuki YOTSUYANAGI Masaki HASHIZUME Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/12/01
Vol. E96-A  No. 12  pp. 2561-2567
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
open faultsadjacent linestest pattern generationcoupling capacitanceSAT-based ATPG
 Summary | Full Text:PDF(590.4KB)

On Detecting Delay Faults Using Time-to-Digital Converter Embedded in Boundary Scan
Hiroyuki YOTSUYANAGI Hiroyuki MAKIMOTO Takanobu NIMIYA Masaki HASHIZUME 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/09/01
Vol. E96-D  No. 9  pp. 1986-1993
Type of Manuscript:  Special Section PAPER (Special Section on Dependable Computing)
Category: 
Keyword: 
delay testingtime-to-digital converterboundary scandesign for testability
 Summary | Full Text:PDF(859.2KB)

Scan Chain Ordering to Reduce Test Data for BIST-Aided Scan Test Using Compatible Scan Flip-Flops
Hiroyuki YOTSUYANAGI Masayuki YAMAMOTO Masaki HASHIZUME 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/01/01
Vol. E93-D  No. 1  pp. 10-16
Type of Manuscript:  Special Section PAPER (Special Section on Test, Diagnosis and Verification of SOCs)
Category: 
Keyword: 
BIST-aided scan testscan chain orderingtest data reductioncompatible flip-flopstest pattern generation
 Summary | Full Text:PDF(427.9KB)

Genetic State Reduction Method of Incompletely Specified Machines
Masaki HASHIZUME Teruyoshi MATSUSHIMA Takashi SHIMAMOTO Hiroyuki YOTSUYANAGI Takeomi TAMESADA Akio SAKAMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/06/01
Vol. E87-A  No. 6  pp. 1555-1563
Type of Manuscript:  PAPER
Category: Graphs and Networks
Keyword: 
incompletely specified machinemaximal compatible setstate reduction
 Summary | Full Text:PDF(470.2KB)

Lead Open Detection Based on Supply Current of CMOS LSIs
Masao TAKAGI Masaki HASHIZUME Masahiro ICHIMIYA Hiroyuki YOTSUYANAGI Takeomi TAMESADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/06/01
Vol. E87-A  No. 6  pp. 1330-1337
Type of Manuscript:  Special Section PAPER (Special Section on Papers Selected from 2003 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2003))
Category: 
Keyword: 
lead openCMOS LSIsupply current testelectric field
 Summary | Full Text:PDF(499.9KB)

Test Sequence Generation for Test Time Reduction of IDDQ Testing
Hiroyuki YOTSUYANAGI Masaki HASHIZUME Takeomi TAMESADA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/03/01
Vol. E87-D  No. 3  pp. 537-543
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSI)
Category: Test Generation and Compaction
Keyword: 
IDDQ testingbridging faultsswitching currentsupply current testCMOS circuits
 Summary | Full Text:PDF(1MB)

Identification and Frequency Estimation of Feedback Bridging Faults Generating Logical Oscillation in CMOS Circuits
Masaki HASHIZUME Hiroyuki YOTSUYANAGI Takeomi TAMESADA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/03/01
Vol. E87-D  No. 3  pp. 571-579
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSI)
Category: Fault Detection
Keyword: 
feedback bridging faultcombinational circuitlogical oscillation
 Summary | Full Text:PDF(564KB)

Test Pattern Generation for CMOS Open Defect Detection by Supply Current Testing under AC Electric Field
Hiroyuki YOTSUYANAGI Taisuke IWAKIRI Masaki HASHIZUME Takeomi TAMESADA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/12/01
Vol. E86-D  No. 12  pp. 2666-2673
Type of Manuscript:  Special Section PAPER (Special Issue on Dependable Computing)
Category: Test
Keyword: 
open defectssupply current testCMOS circuitselectric field
 Summary | Full Text:PDF(576.5KB)

Sequential Redundancy Removal Using Test Generation and Multiple Strongly Unreachable States
Hiroyuki YOTSUYANAGI Masaki HASHIZUME Takeomi TAMESADA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10  pp. 1605-1608
Type of Manuscript:  Special Section LETTER (Special Issue on Test and Verification of VLSI)
Category: 
Keyword: 
synthesis for testabilityredundancy removalsequential circuitundetectable faultsunreachable states
 Summary | Full Text:PDF(220.4KB)

CMOS Open Defect Detection by Supply Current Measurement under Time-Variable Electric Field Supply
Masaki HASHIZUME Masahiro ICHIMIYA Hiroyuki YOTSUYANAGI Takeomi TAMESADA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10  pp. 1542-1550
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: Current Test
Keyword: 
open defectCMOSsupply current testelectric field
 Summary | Full Text:PDF(1.1MB)

IDDQ Test Time Reduction by High Speed Charging of Load Capacitors of CMOS Logic Gates
Masaki HASHIZUME Teppei TAKEDA Masahiro ICHIMIYA Hiroyuki YOTSUYANAGI Yukiya MIURA Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10  pp. 1534-1541
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: Current Test
Keyword: 
IDDQ sensorCMOSIDDQ testbridging fault
 Summary | Full Text:PDF(690.4KB)

Testable Static CMOS PLA for IDDQ Testing
Masaki HASHIZUME Hiroshi HOSHIKA Hiroyuki YOTSUYANAGI Takeomi TAMESADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/06/01
Vol. E84-A  No. 6  pp. 1488-1495
Type of Manuscript:  Special Section PAPER (Special Section on Papers Selected from 2000 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2000))
Category: 
Keyword: 
static PLAtestable designIDDQ testbridging fault
 Summary | Full Text:PDF(575.9KB)

Retiming for Sequential Circuits with a Specified Initial State and Its Application to Testability Enhancement
Hiroyuki YOTSUYANAGI Seiji KAJIHARA Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/07/25
Vol. E78-D  No. 7  pp. 861-867
Type of Manuscript:  Special Section PAPER (Special Issue on Verification, Test and Diagnosis of VLSI Systems)
Category: 
Keyword: 
retiminglogic synthesisredundancy removaltest synthesis
 Summary | Full Text:PDF(542.1KB)