Hiroyuki OCHI


Area-Efficient LUT-Like Programmable Logic Using Atom Switch and Its Delay-Optimal Mapping Algorithm
Toshiki HIGASHI Hiroyuki OCHI 
Publication:   
Publication Date: 2017/07/01
Vol. E100-A  No. 7  pp. 1418-1426
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
field programmable gate arraylook-up tablenon-volatile resistive-change elementtechnology mapping for combinational circuit
 Summary | Full Text:PDF(902.9KB)

Range Limiter Using Connection Bounding Box for SA-Based Placement of Mixed-Grained Reconfigurable Architecture
Takashi KISHIMOTO Wataru TAKAHASHI Kazutoshi WAKABAYASHI Hiroyuki OCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/12/01
Vol. E99-A  No. 12  pp. 2328-2334
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
simulated annealing based placement algorithmcoarse-grained and fine-grained reconfigurable architectures
 Summary | Full Text:PDF(1.6MB)

An Error Correction Scheme through Time Redundancy for Enhancing Persistent Soft-Error Tolerance of CGRAs
Takashi IMAGAWA Masayuki HIROMOTO Hiroyuki OCHI Takashi SATO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2015/07/01
Vol. E98-C  No. 7  pp. 741-750
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
coarse-grained reconfigurable architecturereliabilitytriple modular redundancyimmediate terminationerror-critical period
 Summary | Full Text:PDF(1.4MB)

Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing
Hiroaki KONOURA Dawood ALNAJJAR Yukio MITSUYAMA Hajime SHIMADA Kazutoshi KOBAYASHI Hiroyuki KANBARA Hiroyuki OCHI Takashi IMAGAWA Kazutoshi WAKABAYASHI Masanori HASHIMOTO Takao ONOYE Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/12/01
Vol. E97-A  No. 12  pp. 2518-2529
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
reconfigurable architecturesoft errorradiation testbehavioral synthesisstate machine
 Summary | Full Text:PDF(3.8MB)

Parallel Acceleration Scheme for Monte Carlo Based SSTA Using Generalized STA Processing Element
Hiroshi YUASA Hiroshi TSUTSUI Hiroyuki OCHI Takashi SATO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/04/01
Vol. E96-C  No. 4  pp. 473-481
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
statistical static timing analysisdelay distributionslew ratefield-programmable gate arrayMersenne Twister
 Summary | Full Text:PDF(1.3MB)

A Cost-Effective Selective TMR for Coarse-Grained Reconfigurable Architectures Based on DFG-Level Vulnerability Analysis
Takashi IMAGAWA Hiroshi TSUTSUI Hiroyuki OCHI Takashi SATO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/04/01
Vol. E96-C  No. 4  pp. 454-462
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
soft errorsingle event upsettriple modular redundancyreliabilitysimulated annealing
 Summary | Full Text:PDF(1.4MB)

Bayesian Estimation of Multi-Trap RTN Parameters Using Markov Chain Monte Carlo Method
Hiromitsu AWANO Hiroshi TSUTSUI Hiroyuki OCHI Takashi SATO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A  No. 12  pp. 2272-2283
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Device and Circuit Modeling and Analysis
Keyword: 
random telegraph noiseBayesian estimationMarkov chain Monte Carlodevice characterizationsource separationstatistical machine learning
 Summary | Full Text:PDF(3.3MB)

A Variability-Aware Energy-Minimization Strategy for Subthreshold Circuits
Junya KAWASHIMA Hiroshi TSUTSUI Hiroyuki OCHI Takashi SATO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A  No. 12  pp. 2242-2250
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Device and Circuit Modeling and Analysis
Keyword: 
subthreshold operationprocess variationminimum operation voltage estimationenergy minimizationyield maximization
 Summary | Full Text:PDF(837.1KB)

Reliability Evaluation Environment for Exploring Design Space of Coarse-Grained Reconfigurable Architectures
Takashi IMAGAWA Masayuki HIROMOTO Hiroyuki OCHI Takashi SATO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/12/01
Vol. E93-A  No. 12  pp. 2524-2532
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
soft errorTMRreliabilitymethodology
 Summary | Full Text:PDF(653KB)

Hardware Accelerator for Run-Time Learning Adopted in Object Recognition with Cascade Particle Filter
Hiroki SUGANO Hiroyuki OCHI Yukihiro NAKAMURA Ryusuke MIYAMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/11/01
Vol. E92-A  No. 11  pp. 2801-2808
Type of Manuscript:  Special Section PAPER (Special Section on Smart Multimedia & Communication Systems)
Category: Image Processing
Keyword: 
Cascade Particle Filterhardware acceleratorembedded systemsreal-time processing
 Summary | Full Text:PDF(691.3KB)

Efficient Memory Organization Framework for JPEG2000 Entropy Codec
Hiroki SUGANO Takahiko MASUZAKI Hiroshi TSUTSUI Takao ONOYE Hiroyuki OCHI Yukihiro NAKAMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/08/01
Vol. E92-A  No. 8  pp. 1970-1977
Type of Manuscript:  Special Section PAPER (Special Section on Signal Processing)
Category: Realization
Keyword: 
JPEG2000entropy codechardwarememory organization
 Summary | Full Text:PDF(600KB)

Autonomous Repair Fault Tolerant Dynamic Reconfigurable Device
Kentaro NAKAHARA Shin'ichi KOUYAMA Tomonori IZUMI Hiroyuki OCHI Yukihiro NAKAMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12  pp. 3612-3621
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Embedded, Real-Time and Reconfigurable Systems
Keyword: 
fault tolerancedependableFPGAreconfigurable devicesoft error
 Summary | Full Text:PDF(633.8KB)

A Simulation Platform for Designing Cell-Array-Based Self-Reconfigurable Architecture
Shin'ichi KOUYAMA Tomonori IZUMI Hiroyuki OCHI Yukihiro NAKAMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/04/01
Vol. E90-A  No. 4  pp. 784-791
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
self-reconfigurationevaluation of architecturemodel of architecturesimulation
 Summary | Full Text:PDF(621.2KB)

Fault Tolerant Dynamic Reconfigurable Device Based on EDAC with Rollback
Kentaro NAKAHARA Shin'ichi KOUYAMA Tomonori IZUMI Hiroyuki OCHI Yukihiro NAKAMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12  pp. 3652-3658
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Architecture
Keyword: 
fault tolerancedependabledynamic reconfigurable
 Summary | Full Text:PDF(424.6KB)

A Localization Scheme for Sensor Networks Based on Wireless Communication with Anchor Groups
Hiroyuki OCHI Shigeaki TAGASHIRA Satoshi FUJITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/05/01
Vol. E89-D  No. 5  pp. 1614-1621
Type of Manuscript:  Special Section PAPER (Special Section on Challenges in Ad-hoc and Multi-hop Wireless Communications)
Category: 
Keyword: 
sensor networkslocalizationrange-freenesspoint-in-triangulation testBluetooth
 Summary | Full Text:PDF(261.6KB)

An Integrated Approach of Variable Ordering and Logic Mapping into LUT-Array-Based PLD
Tomonori IZUMI Shin'ichi KOUYAMA Hiroyuki OCHI Yukihiro NAKAMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/04/01
Vol. E88-A  No. 4  pp. 907-914
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
reconfigurable systemdesign technologylogic synthesisvariable orderinglook-up table
 Summary | Full Text:PDF(2.1MB)

Development of an IP Library of IEEE-754-Standard Single-Precision Floating-Point Dividers
Hiroyuki OCHI Tatsuya SUZUKI Sayaka MATSUNAGA Yoichi KAWANO Takao TSUDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12  pp. 3020-3027
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: IP Design
Keyword: 
SRT methodrestoring methodperformance-area ratioperformance-power ratio
 Summary | Full Text:PDF(561.9KB)

Datapath-Layout-Driven Design for Low-Power Standard-Cell LSI Implementation
Takahiro KAKIMOTO Hiroyuki OCHI Takao TSUDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A  No. 12  pp. 2795-2798
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Design
Keyword: 
low power designwire lengthfloorplanbit sliceone-hot code
 Summary | Full Text:PDF(255KB)

An Algorithm for Generating Generic BDDs
Tetsushi KATAYAMA Hiroyuki OCHI Takao TSUDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12  pp. 2505-2512
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
combinational synthesislogic functionswitching theorybinary decision diagrampass-transistor logic
 Summary | Full Text:PDF(632.9KB)

ASAver.1: An FPGA-Based Education Board for Computer Architecture/System Design
Hiroyuki OCHI Yoko KAMIDOI Hideyuki KAWABATA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A  No. 10  pp. 1826-1833
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
education of computer architecturesystem designDLX-like pipelined RISC processorfield-programmable gate arrayverilog-HDL
 Summary | Full Text:PDF(1020.4KB)

A Zero-Suppressed BDD Package with Pruning and Its Application to GRM Minimization
Hiroyuki OCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/12/25
Vol. E79-A  No. 12  pp. 2134-2139
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
zero-suppressed binary decision diagram (ZBDD)implementation of BDD packageAND-EXOR logic minimizationgeneralized Reed-Muller expression
 Summary | Full Text:PDF(490.9KB)

An Exact Minimization of AND-EXOR Expressions Using Encoded MRCF
Hiroyuki OCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/12/25
Vol. E79-A  No. 12  pp. 2131-2133
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
logic cptimizationexact minimization of AND-EXOR expressionsHelliwell equationO-suppressed binary decision diagrams
 Summary | Full Text:PDF(239.4KB)

Formal Design Verification of Combinational Circuits Specified by Recurrence Equations
Hiroyuki OCHI Shuzo YAJIMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/10/25
Vol. E79-D  No. 10  pp. 1431-1435
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Design Verification
Keyword: 
formal design verificationbinary decision diagramarithmetic circuitsspecificationrecurrence equations
 Summary | Full Text:PDF(401.9KB)