IEICE SEARCH SYSTEM

Hiroyuki OCHI

Parallel Acceleration Scheme for Monte Carlo Based SSTA Using Generalized STA Processing Element Hiroshi YUASA Hiroshi TSUTSUI Hiroyuki OCHI Takashi SATO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2013/04/01 Vol. E96-C No. 4 pp. 473-481 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology) Category: Keyword: statistical static timing analysis, delay distribution, slew rate, field-programmable gate array, Mersenne Twister,
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A Cost-Effective Selective TMR for Coarse-Grained Reconfigurable Architectures Based on DFG-Level Vulnerability Analysis Takashi IMAGAWA Hiroshi TSUTSUI Hiroyuki OCHI Takashi SATO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2013/04/01 Vol. E96-C No. 4 pp. 454-462 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology) Category: Keyword: soft error, single event upset, triple modular redundancy, reliability, simulated annealing,
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Bayesian Estimation of Multi-Trap RTN Parameters Using Markov Chain Monte Carlo Method Hiromitsu AWANO Hiroshi TSUTSUI Hiroyuki OCHI Takashi SATO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/12/01 Vol. E95-A No. 12 pp. 2272-2283 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Device and Circuit Modeling and Analysis Keyword: random telegraph noise, Bayesian estimation, Markov chain Monte Carlo, device characterization, source separation, statistical machine learning,
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A Variability-Aware Energy-Minimization Strategy for Subthreshold Circuits Junya KAWASHIMA Hiroshi TSUTSUI Hiroyuki OCHI Takashi SATO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/12/01 Vol. E95-A No. 12 pp. 2242-2250 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Device and Circuit Modeling and Analysis Keyword: subthreshold operation, process variation, minimum operation voltage estimation, energy minimization, yield maximization,
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Reliability Evaluation Environment for Exploring Design Space of Coarse-Grained Reconfigurable Architectures Takashi IMAGAWA Masayuki HIROMOTO Hiroyuki OCHI Takashi SATO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/12/01 Vol. E93-A No. 12 pp. 2524-2532 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: soft error, TMR, reliability, methodology,
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Hardware Accelerator for Run-Time Learning Adopted in Object Recognition with Cascade Particle Filter Hiroki SUGANO Hiroyuki OCHI Yukihiro NAKAMURA Ryusuke MIYAMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/11/01 Vol. E92-A No. 11 pp. 2801-2808 Type of Manuscript: Special Section PAPER (Special Section on Smart Multimedia & Communication Systems) Category: Image Processing Keyword: Cascade Particle Filter, hardware accelerator, embedded systems, real-time processing,
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Efficient Memory Organization Framework for JPEG2000 Entropy Codec Hiroki SUGANO Takahiko MASUZAKI Hiroshi TSUTSUI Takao ONOYE Hiroyuki OCHI Yukihiro NAKAMURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/08/01 Vol. E92-A No. 8 pp. 1970-1977 Type of Manuscript: Special Section PAPER (Special Section on Signal Processing) Category: Realization Keyword: JPEG2000, entropy codec, hardware, memory organization,
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Autonomous Repair Fault Tolerant Dynamic Reconfigurable Device Kentaro NAKAHARA Shin'ichi KOUYAMA Tomonori IZUMI Hiroyuki OCHI Yukihiro NAKAMURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/12/01 Vol. E91-A No. 12 pp. 3612-3621 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Embedded, Real-Time and Reconfigurable Systems Keyword: fault tolerance, dependable, FPGA, reconfigurable device, soft error,
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A Simulation Platform for Designing Cell-Array-Based Self-Reconfigurable Architecture Shin'ichi KOUYAMA Tomonori IZUMI Hiroyuki OCHI Yukihiro NAKAMURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/04/01 Vol. E90-A No. 4 pp. 784-791 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: self-reconfiguration, evaluation of architecture, model of architecture, simulation,
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Fault Tolerant Dynamic Reconfigurable Device Based on EDAC with Rollback Kentaro NAKAHARA Shin'ichi KOUYAMA Tomonori IZUMI Hiroyuki OCHI Yukihiro NAKAMURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/12/01 Vol. E89-A No. 12 pp. 3652-3658 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: VLSI Architecture Keyword: fault tolerance, dependable, dynamic reconfigurable,
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A Localization Scheme for Sensor Networks Based on Wireless Communication with Anchor Groups Hiroyuki OCHI Shigeaki TAGASHIRA Satoshi FUJITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2006/05/01 Vol. E89-D No. 5 pp. 1614-1621 Type of Manuscript: Special Section PAPER (Special Section on Challenges in Ad-hoc and Multi-hop Wireless Communications) Category: Keyword: sensor networks, localization, range-freeness, point-in-triangulation test, Bluetooth,
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An Integrated Approach of Variable Ordering and Logic Mapping into LUT-Array-Based PLD Tomonori IZUMI Shin'ichi KOUYAMA Hiroyuki OCHI Yukihiro NAKAMURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/04/01 Vol. E88-A No. 4 pp. 907-914 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: reconfigurable system, design technology, logic synthesis, variable ordering, look-up table,
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Development of an IP Library of IEEE-754-Standard Single-Precision Floating-Point Dividers Hiroyuki OCHI Tatsuya SUZUKI Sayaka MATSUNAGA Yoichi KAWANO Takao TSUDA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-A No. 12 pp. 3020-3027 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: IP Design Keyword: SRT method, restoring method, performance-area ratio, performance-power ratio,
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Datapath-Layout-Driven Design for Low-Power Standard-Cell LSI Implementation Takahiro KAKIMOTO Hiroyuki OCHI Takao TSUDA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/12/01 Vol. E85-A No. 12 pp. 2795-2798 Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms) Category: VLSI Design Keyword: low power design, wire length, floorplan, bit slice, one-hot code,
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An Algorithm for Generating Generic BDDs Tetsushi KATAYAMA Hiroyuki OCHI Takao TSUDA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/12/20 Vol. E83-A No. 12 pp. 2505-2512 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis Keyword: combinational synthesis, logic function, switching theory, binary decision diagram, pass-transistor logic,
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ASAver.1: An FPGA-Based Education Board for Computer Architecture/System Design Hiroyuki OCHI Yoko KAMIDOI Hideyuki KAWABATA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/10/20 Vol. E80-A No. 10 pp. 1826-1833 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: education of computer architecture, system design, DLX-like pipelined RISC processor, field-programmable gate array, verilog-HDL,
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An Exact Minimization of AND-EXOR Expressions Using Encoded MRCF Hiroyuki OCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1996/12/20 Vol. E79-A No. 12 pp. 2131-2133 Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: logic cptimization, exact minimization of AND-EXOR expressions, Helliwell equation, O-suppressed binary decision diagrams,
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A Zero-Suppressed BDD Package with Pruning and Its Application to GRM Minimization Hiroyuki OCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1996/12/20 Vol. E79-A No. 12 pp. 2134-2139 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: zero-suppressed binary decision diagram (ZBDD), implementation of BDD package, AND-EXOR logic minimization, generalized Reed-Muller expression,
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Formal Design Verification of Combinational Circuits Specified by Recurrence Equations Hiroyuki OCHI Shuzo YAJIMA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1996/10/20 Vol. E79-D No. 10 pp. 1431-1435 Type of Manuscript: Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design) Category: Design Verification Keyword: formal design verification, binary decision diagram, arithmetic circuits, specification, recurrence equations,
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