Hiroyuki MIZUNO

µI/O Architecture: A Power-Aware Interconnect Circuit Design for SoC and SiP
Yusuke KANNO  Hiroyuki MIZUNO  Nobuhiro OODAIRA  Yoshihiko YASU  Kazumasa YANAGISAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/04/01
Vol. E87-C  No. 4  pp. 589-597
Type of Manuscript: Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)
Category: 
Keyword: 
low-cost,  System-on-Chip,  SoC,  System-in-Package,  SiP,  hierarchical I/O design,  signal-level converter,  signal wall function,  low-power,  interconnect circuit, 
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A 100 MIPS High Speed and Low Power Digital Signal Processor
Hiroshi TAKAHASHI  Shigeshi ABIKO  Shintaro MIZUSHIMA  Yuji OZAWA  Kenichi TASHIRO  Shigetoshi MURAMATSU  Masahiro FUSUMADA  Akemi TODOROKI  Youichi TANAKA  Masayasu ITOIGAWA  Isao MORIOKA  Hiroyuki MIZUNO  Miki KOJIMA  Giovanni NASO  Emmanuel EGO  Frank CHIRAT 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/12/20
Vol. E80-C  No. 12  pp. 1546-1552
Type of Manuscript: Special Section PAPER (Special Issue on Low-Power and High-Speed LSI Technologies)
Category: 
Keyword: 
100 MIPS,  digital signal processing,  high speed,  low power,  CPU, 
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Driving Source-Line Cell Architecture for Sub-1-V High-Speed Low-Power Applications
Hiroyuki MIZUNO  Takahiro NAGANO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/07/20
Vol. E79-C  No. 7  pp. 963-968
Type of Manuscript: Special Section PAPER (Special Issue on the 1995 Symposium on VLSI Circuits (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.31, No.4 April 1996))
Category: Memory
Keyword: 
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