Hiroto YASUURA


Short Term Cell-Flipping Technique for Mitigating SNM Degradation Due to NBTI
Yuji KUNITAKE Toshinori SATO Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/04/01
Vol. E94-C  No. 4  pp. 520-529
Type of Manuscript:  Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category: 
Keyword: 
NBTISRAMstatic noise marginstress probabilityregister filecache memory
 Summary | Full Text:PDF(1.2MB)

Enhancements of a Circuit-Level Timing Speculation Technique and Their Evaluations Using a Co-simulation Environment
Yuji KUNITAKE Kazuhiro MIMA Toshinori SATO Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/04/01
Vol. E92-C  No. 4  pp. 483-491
Type of Manuscript:  Special Section PAPER (Special Section on Low-Leakage, Low-Voltage, Low-Power and High-Speed Technologies for System LSIs in Deep-Submicron Era)
Category: 
Keyword: 
worst-case designtiming errorco-simulationparameter variation
 Summary | Full Text:PDF(820.5KB)

A Multi-Application Smart Card System with Authentic Post-Issuance Program Modification
Mohammad Mesbah UDDIN Yasunobu NOHARA Daisuke IKEDA Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/01/01
Vol. E91-A  No. 1  pp. 229-235
Type of Manuscript:  Special Section PAPER (Special Section on Cryptography and Information Security)
Category: Implementation
Keyword: 
smart cardscryptographic protocols for smart cardsmulti-application smart cardssecurityauthentication
 Summary | Full Text:PDF(737.7KB)

FOREWORD
Hiroto YASUURA Shoji KAWAHITO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/08/01
Vol. E88-C  No. 8  pp. 1704-1704
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF(56.4KB)

Bitwidth Optimization for Low Power Digital FIR Filter Design
Kosuke TARUMI Akihiko HYODO Masanori MUROYAMA Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/04/01
Vol. E88-A  No. 4  pp. 869-875
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
low power designbitwidth optimizationdigital FIR filter
 Summary | Full Text:PDF(526.9KB)

A Power Reduction Scheme for Data Buses by Dynamic Detection of Active Bits
Masanori MUROYAMA Akihiko HYODO Takanori OKUMA Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/04/01
Vol. E87-C  No. 4  pp. 598-605
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)
Category: 
Keyword: 
active bitlow powerdatapathdata busdynamic
 Summary | Full Text:PDF(421.1KB)

Power Analysis and Estimation for SOC Design: Techniques and Tools
Yun CAO Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/02/01
Vol. E87-A  No. 2  pp. 410-416
Type of Manuscript:  REVIEW PAPER
Category: VLSI Design Technology and CAD
Keyword: 
low powerSOCpower analysispower estimation
 Summary | Full Text:PDF(248.6KB)

Variable Pipeline Depth Processor for Energy Efficient Systems
Akihiko HYODO Masanori MUROYAMA Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12  pp. 2983-2990
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Power Optimization
Keyword: 
energy efficient designvariable pipeline depthdynamic pipeline and voltage scalingoptimal pipelining
 Summary | Full Text:PDF(1.9MB)

Leakage Power Reduction for Battery-Operated Portable Systems
Yun CAO Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12  pp. 3200-3203
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: Power Optimization
Keyword: 
bitwidth optimizationleakage power reductiondynamic power reduction
 Summary | Full Text:PDF(318.9KB)

Routing Methodology for Minimizing Crosstalk in SoC
Takashi YAMADA Atsushi SAKAI Yoshifumi MATSUSHITA Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/09/01
Vol. E86-A  No. 9  pp. 2347-2356
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
SoCsignal integritycrosstalkinterconnecttiming analysis
 Summary | Full Text:PDF(1.8MB)

Pre-Route Power Analysis Techniques for SoC
Takashi YAMADA Takeshi SAKAMOTO Shinji FURUICHI Mamoru MUKUNO Yoshifumi MATSUSHITA Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/03/01
Vol. E86-A  No. 3  pp. 686-692
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
SoCpower analysisgate-levelcustom wire load model
 Summary | Full Text:PDF(763.6KB)

Low-Power Architecture of a Digital Matched Filter for Direct-Sequence Spread-Spectrum Systems
Takashi YAMADA Shoji GOTO Norihisa TAKAYAMA Yoshifumi MATSUSHITA Yasoo HARADA Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/01/01
Vol. E86-C  No. 1  pp. 79-88
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
matched filterspread-spectrumWCDMAVLSIlow power
 Summary | Full Text:PDF(987.9KB)

Quality-Driven Design for Video Applications
Yun CAO Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A  No. 12  pp. 2568-2576
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Design Methodology
Keyword: 
quality-driven designvariable analysisdesign reuseapplication-specific optimization
 Summary | Full Text:PDF(735.8KB)

Memory Organization for Low-Energy Processor-Based Application-Specific Systems
Yun CAO Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/08/01
Vol. E85-C  No. 8  pp. 1616-1624
Type of Manuscript:  PAPER
Category: Optoelectronics
Keyword: 
low energymemory organizationvariable analysisapplication-specific system
 Summary | Full Text:PDF(578.5KB)

Optimization of Test Accesses with a Combined BIST and External Test Scheme
Makoto SUGIHARA Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11  pp. 2731-2738
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Test
Keyword: 
test timeBISTexternal testCBETtest schedulingtest accesstest busexternal pins
 Summary | Full Text:PDF(720KB)

Towards the System LSI Design Technology
Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/01/01
Vol. E84-A  No. 1  pp. 91-97
Type of Manuscript:  INVITED PAPER (Special Section on the 10th Anniversary of the IEICE Transactions of Fundamentals: "Last Decade and 21st Century")
Category: 
Keyword: 
system LSIsystem on a chipembedded systemsoft-core processor
 Summary | Full Text:PDF(377.6KB)

Synthesis of Minimum-Cost Multilevel Logic Networks via Genetic Algorithm
Barry SHACKLEFORD Etsuko OKUSHI Mitsuhiro YASUDA Hisao KOIZUMI Katsuhiko SEO Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12  pp. 2528-2537
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
genetic algorithmlogic synthesishardware acceleration
 Summary | Full Text:PDF(1.1MB)

System LSI Design Methods for Low Power LSIs
Hiroto YASUURA Tohru ISHIHARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2000/02/25
Vol. E83-C  No. 2  pp. 143-152
Type of Manuscript:  INVITED PAPER (Special Issue on Low-Power High-Speed CMOS LSI Technologies)
Category: 
Keyword: 
low power designsystem leveloptimizationhardware/software codesign
 Summary | Full Text:PDF(801.9KB)

FOREWORD
Hiroto YASUURA Mitsumasa KOYANAGI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11  pp. 2317-2317
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF(202.7KB)

A Memory Power Optimization Technique for Application Specific Embedded Systems
Tohru ISHIHARA Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11  pp. 2366-2374
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
low power designhardware/software codesignmemoryembedded system
 Summary | Full Text:PDF(1.3MB)

A Test Methodology for Core-Based System LSIs
Makoto SUGIHARA Hiroshi DATE Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12  pp. 2640-2645
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Test
Keyword: 
testing timecore-based system LSIBISTexternal testing
 Summary | Full Text:PDF(584.1KB)

Program Slicing on VHDL Descriptions and Its Evaluation
Shigeru ICHINOSE Mizuho IWAIHARA Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12  pp. 2585-2594
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Design Reuse
Keyword: 
hardware description languageVHDLprogram slicingdesign reusecomponent extraction
 Summary | Full Text:PDF(853.1KB)

Module Selection Using Manufacturing Information
Hiroyuki TOMIYAMA Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12  pp. 2576-2584
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-level Synthesis
Keyword: 
high-level synthesismodule selectionmanufacturabilityyield
 Summary | Full Text:PDF(796.4KB)

Language and Compiler for Optimizing Datapath Widths of Embedded Systems
Akihiko INOUE Hiroyuki TOMIYAMA Takanori OKUMA Hiroyuki KANBARA Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12  pp. 2595-2604
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Co-design
Keyword: 
embedded system designhardware/software codesignretargetable compiler
 Summary | Full Text:PDF(899.6KB)

Instruction Scheduling to Reduce Switching Activity of Off-Chip Buses for Low-Power Systems with Caches
Hiroyuki TOMIYAMA Tohru ISHIHARA Akihiko INOUE Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12  pp. 2621-2629
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Compiler
Keyword: 
compiler optimizationinstruction schedulinglow powercaches
 Summary | Full Text:PDF(762.4KB)

Programmable Power Management Architecture for Power Reduction
Tohru ISHIHARA Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/09/25
Vol. E81-C  No. 9  pp. 1473-1480
Type of Manuscript:  Special Section PAPER (Special Issue on Novel VLSI Processor Architectures)
Category: 
Keyword: 
low power designpower managementCMOS VLSI processor
 Summary | Full Text:PDF(677.5KB)

Soft-Core Processor Architecture for Embedded System Design
Eko Fajar NURPRASETYO Akihiko INOUE Hiroyuki TOMIYAMA Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/09/25
Vol. E81-C  No. 9  pp. 1416-1423
Type of Manuscript:  Special Section PAPER (Special Issue on Novel VLSI Processor Architectures)
Category: 
Keyword: 
scalable processordatapath widthmemory
 Summary | Full Text:PDF(754.9KB)

Embedded System Cost Optimization via Data Path Width Adjustment
Barry SHACKLEFORD Mitsuhiro YASUDA Etsuko OKUSHI Hisao KOIZUMI Hiroyuki TOMIYAMA Akihiko INOUE Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/10/25
Vol. E80-D  No. 10  pp. 974-981
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: High Level Synthesis
Keyword: 
embedded systemssystem on chipCPUmemory
 Summary | Full Text:PDF(757.2KB)

Experimental Analysis of Power Estimation Models of CMOS VLSI Circuits
Tohru ISHIHARA Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/03/25
Vol. E80-A  No. 3  pp. 480-486
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
CMOS VLSI circuitslow power designpower estimation
 Summary | Full Text:PDF(520.2KB)

Satsuki: An Integrated Processor Synthesis and Compiler Generation System
Barry SHACKLEFORD Mitsuhiro YASUDA Etsuko OKUSHI Hisao KOIZUMI Hiroyuki TOMIYAMA Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/10/25
Vol. E79-D  No. 10  pp. 1373-1381
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Hardware-Software Codesign
Keyword: 
computer aided designsystem designprocessor designcompiler generation
 Summary | Full Text:PDF(903.5KB)

FOREWORD
Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/10/25
Vol. E79-D  No. 10  pp. 1371-1372
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF(108.9KB)

A Proposal for a Co-design Method in Control Systems Using Combination of Models
Hisao KOIZUMI Katsuhiko SEO Fumio SUZUKI Yoshisuke OHTSURU Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/03/25
Vol. E78-D  No. 3  pp. 237-247
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: System Design
Keyword: 
co-designmodelingvirtual instrumentreplacement method
 Summary | Full Text:PDF(978KB)

FOREWORD
Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/03/25
Vol. E78-D  No. 3  pp. 197-198
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF(102.3KB)

COACH:A Computer Aided Design Tool for Computer Architects
Hiroki AKABOSHI Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/10/25
Vol. E76-A  No. 10  pp. 1760-1769
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
computer aided designcomputer architecture designperformance evaluationcompiler generation
 Summary | Full Text:PDF(765.3KB)

A Language for Designing Module Generators
Vasily G. MOSHNYAGA Keikichi TAMARU Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/09/25
Vol. E76-D  No. 9  pp. 1066-1074
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Hardware Design Languages
Keyword: 
module generatorhardware disign language
 Summary | Full Text:PDF(722.8KB)

FOREWORD
Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/09/25
Vol. E76-D  No. 9  pp. 989-990
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF(95.2KB)

A Bit-Parallel Block-Parallel Functional Memory Type Parallel Processor Architecture
Kazutoshi KOBAYASHI Keikichi TAMARU Hiroto YASUURA Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/07/25
Vol. E76-C  No. 7  pp. 1151-1158
Type of Manuscript:  Special Section PAPER (Special Issue on New Architecture LSIs)
Category: Memory-Based Parallel Processor Architectures
Keyword: 
parallel processormemory-based simple structurelogical and arithmetic operations
 Summary | Full Text:PDF(734.9KB)

Extraction of Behavioral Descriptions from Synchronous Sequential Circuits
Masahiko OHMURA Hiroto YASUURA Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/10/25
Vol. E75-A  No. 10  pp. 1239-1246
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
behavioral extractionlogic verification
 Summary | Full Text:PDF(580KB)

An Architecture for FFT Butterfly Computation with Merged Core Multiplication technique
Farhad Fuad ISLAM Hiroto YASUURA Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1990/11/25
Vol. E73-E  No. 11  pp. 1810-1812
Type of Manuscript:  Special Section LETTER (Special Issue on 1990 Autumn Natl. Conv. IEICE)
Category: Signals, Circuits and Images
Keyword: 
 Summary | Full Text:PDF(180.2KB)