Hiroshi YAMADA


Examination of TMV First Process for FO-WLP with Cu Pillar Substrate
Hiroshi YAMADA Akihiko HAPPOYA Shuzo AKEJIMA Hirokazu EZAWA 
Publication:   - - Abstracts of (Japanese Edition)
Publication Date: 2018/02/01
Vol. J101-C  No. 2  pp. 66-73
Type of Manuscript:  Special Section PAPER (Special Section on Heterogeneous Integration Packaging Technologies Realizing Next Generation Mobility Devices)
Category: 
Keyword: 
Fan out wafer level packageThrough mold viaCu pillarTMV first processresidue of the resin
 Summary | Full Text(in Japanese):PDF(4.3MB)

S-parameter Degradation of GaAS FET against Irradiation of Surface Activation Process
Masahisa FUJINO Tadatomo SUGA Nobuto MANAGAKI Hiroshi YAMADA 
Publication:   C - Abstracts of IEICE TRANSACTIONS on Electronics (Japanese Edition)
Publication Date: 2016/11/01
Vol. J99-C  No. 11  pp. 501-507
Type of Manuscript:  Special Section PAPER (Special Section on High-functionality and High-density Packaging Technologies for Next Generation Mobility Applications)
Category: 
Keyword: 
surface activated bonding3D packagingrelaibility of FETMMIC
 Summary | Full Text(in Japanese):PDF(1.4MB)

Trends and Future Technology Direction of Wafer Level Chip Scale Packages
Hiroshi YAMADA 
Publication:   C - Abstracts of IEICE TRANSACTIONS on Electronics (Japanese Edition)
Publication Date: 2009/11/01
Vol. J92-C  No. 11  pp. 595-605
Type of Manuscript:  Special Section PAPER (Special Issue on Advanced Packging and Environmentally Conscious Packaging Technologies in Next-Generation Electronic Equipment)
Category: 
Keyword: 
wafer level chip scale packageredistribution layer processbump processunderfill encapsulation processwafer level system integration package
 Summary | Full Text(in Japanese):PDF(2.1MB)