Hiroshi TAKAHASHI


Design and Experimental Evaluation of 60GHz Multiuser Gigabit/s Small Cell Radio Access Based on IEEE 802.11ad/WiGig
Koji TAKINAMI Naganori SHIRAKATA Masashi KOBAYASHI Tomoya URUSHIHARA Hiroshi TAKAHASHI Hiroyuki MOTOZUKA Masataka IRIE Masayuki SHIMIZU Yuji TOMISAWA Kazuaki TAKAHASHI 
Publication:   
Publication Date: 2017/07/01
Vol. E100-B  No. 7  pp. 1075-1085
Type of Manuscript:  Special Section PAPER (Special Section on Smart Radio and Its Applications in Conjunction with Main Topics of SmartCom)
Category: Terrestrial Wireless Communication/Broadcasting Technologies
Keyword: 
IEEE 802.11adWiGig60 GHzsmall cellheterogeneous network5G cellular network
 Summary | Full Text:PDF(6.2MB)

A 60 GHz Hybrid Analog/Digital Beamforming Receiver with Interference Suppression for Multiuser Gigabit/s Radio Access
Koji TAKINAMI Hiroyuki MOTOZUKA Tomoya URUSHIHARA Masashi KOBAYASHI Hiroshi TAKAHASHI Masataka IRIE Takenori SAKAMOTO Yohei MORISHITA Kenji MIYANAGA Takayuki TSUKIZAWA Noriaki SAITO Naganori SHIRAKATA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2016/07/01
Vol. E99-C  No. 7  pp. 856-865
Type of Manuscript:  PAPER
Category: Microwaves, Millimeter-Waves
Keyword: 
IEEE 802.11adWiGig60 GHzdirect conversionCMOSbeamforminginterference suppressioninterference rejection combining
 Summary | Full Text:PDF(2.2MB)

FOREWORD
Hiroshi TAKAHASHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/09/01
Vol. E96-D  No. 9  pp. 1905-1906
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF(81.2KB)

Test Generation for Delay Faults on Clock Lines under Launch-on-Capture Test Environment
Yoshinobu HIGAMI Hiroshi TAKAHASHI Shin-ya KOBAYASHI Kewal K. SALUJA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/06/01
Vol. E96-D  No. 6  pp. 1323-1331
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
test generationfault simulationclock linedelay fault
 Summary | Full Text:PDF(595KB)

Generation of Diagnostic Tests for Transition Faults Using a Stuck-At ATPG Tool
Yoshinobu HIGAMI Satoshi OHNO Hironori YAMAOKA Hiroshi TAKAHASHI Yoshihiro SHIMIZU Takashi AIKYO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/04/01
Vol. E95-D  No. 4  pp. 1093-1100
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
fault diagnosistest generationtransition faultsstuck-at ATPG
 Summary | Full Text:PDF(502.5KB)

Compact and Athermal DQPSK Demodulator with Silica-Based Planar Lightwave Circuit
Yusuke NASU Yohei SAKAMAKI Kuninori HATTORI Shin KAMEI Toshikazu HASHIMOTO Takashi SAIDA Hiroshi TAKAHASHI Yasuyuki INOUE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/07/01
Vol. E93-C  No. 7  pp. 1191-1198
Type of Manuscript:  PAPER
Category: Optoelectronics
Keyword: 
differential quadrature phase-shift keying (DQPSK)Mach-ZehnderDelay-line interferometeroptical planar waveguides
 Summary | Full Text:PDF(2.6MB)

Addressing Defect Coverage through Generating Test Vectors for Transistor Defects
Yoshinobu HIGAMI Kewal K. SALUJA Hiroshi TAKAHASHI Shin-ya KOBAYASHI Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12  pp. 3128-3135
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verfication
Keyword: 
test generationtransistor defectsstuck-at testsdefect coverage
 Summary | Full Text:PDF(299.6KB)

Maximizing Stuck-Open Fault Coverage Using Stuck-at Test Vectors
Yoshinobu HIGAMI Kewal K. SALUJA Hiroshi TAKAHASHI Shin-ya KOBAYASHI Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12  pp. 3506-3513
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
fault simulationtest generationstuck-open faultsstuck-at testsdefect coverage
 Summary | Full Text:PDF(283.9KB)

Fault Simulation and Test Generation for Transistor Shorts Using Stuck-at Test Tools
Yoshinobu HIGAMI Kewal K. SALUJA Hiroshi TAKAHASHI Shin-ya KOBAYASHI Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/03/01
Vol. E91-D  No. 3  pp. 690-699
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSIs)
Category: Defect-Based Testing
Keyword: 
transistor shortfault simulationtest generationstuck-at test tool
 Summary | Full Text:PDF(346.3KB)

Post-BIST Fault Diagnosis for Multiple Faults
Hiroshi TAKAHASHI Yoshinobu HIGAMI Shuhei KADOYAMA Yuzo TAKAMATSU Koji YAMAZAKI Takashi AIKYO Yasuo SATO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/03/01
Vol. E91-D  No. 3  pp. 771-775
Type of Manuscript:  Special Section LETTER (Special Section on Test and Verification of VLSIs)
Category: 
Keyword: 
post-BIST fault diagnosismultiple stuck-at faultscombinational circuitspass/fail information
 Summary | Full Text:PDF(88.5KB)

Fault Diagnosis on Multiple Fault Models by Using Pass/Fail Information
Yuzo TAKAMATSU Hiroshi TAKAHASHI Yoshinobu HIGAMI Takashi AIKYO Koji YAMAZAKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/03/01
Vol. E91-D  No. 3  pp. 675-682
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSIs)
Category: Fault Diagnosis
Keyword: 
diagnosisfault modelfault locationfault simulationcombinational circuitspass/fail information
 Summary | Full Text:PDF(491.4KB)

Low-Phase Noise Photonic Millimeter-Wave Generator Using an AWG Integrated with a 3-dB Combiner
Akihiko HIRATA Hiroyoshi TOGO Naofumi SHIMIZU Hiroshi TAKAHASHI Katsunari OKAMOTO Tadao NAGATSUMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/07/01
Vol. E88-C  No. 7  pp. 1458-1464
Type of Manuscript:  Special Section PAPER (Special Section on Recent Technologies of Microwave and Millimeter-Wave Devices Focusing on Miniaturization and Advancement in Performance with Their Applications)
Category: Millimeter-Wave Technologies
Keyword: 
photonic millimeter-wave generatorplanar lightwave circuitarrayed-waveguide gratingphase noise
 Summary | Full Text:PDF(1.1MB)

A 1.5 V, 200 MHz, 400 MIPS, 188 µA/MHz and 1.2 V, 300 MHz, 600 MIPS, 169 µA/MHz Digital Signal Processor Core for 3G Wireless Applications
Hiroshi TAKAHASHI Shigeshi ABIKO Kenichi TASHIRO Kaoru AWAKA Yutaka TOYONOH Rimon IKENO Shigetoshi MURAMATSU Yasumasa IKEZAKI Tsuyoshi TANAKA Akihiro TAKEGAMA Hiroshi KIMIZUKA Hidehiko NITTA Miki KOJIMA Masaharu SUZUKI James Lowell LARIMER 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/04/01
Vol. E87-C  No. 4  pp. 491-501
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)
Category: 
Keyword: 
200 MHz300 MHz400 MIPS600 MIPShigh-speedlow-powerfixed point DSP130 nm
 Summary | Full Text:PDF(2.4MB)

An Alternative Test Generation for Path Delay Faults by Using Ni-Detection Test Sets
Hiroshi TAKAHASHI Kewal K. SALUJA Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/12/01
Vol. E86-D  No. 12  pp. 2650-2658
Type of Manuscript:  Special Section PAPER (Special Issue on Dependable Computing)
Category: Test
Keyword: 
test generationpath delay faults N-propagation test-pair setcombinational circuits
 Summary | Full Text:PDF(587.1KB)

High-Speed and Low-Power Techniques of Hardware and Software for Digital Signal Processors
Hiroshi TAKAHASHI Rimon IKENO Yutaka TOYONOH Akihiro TAKEGAMA Yasumasa IKEZAKI Tohru URASAKI Hitoshi SATOH Masayasu ITOIGAWA Yoshinari MATSUMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/04/01
Vol. E86-C  No. 4  pp. 589-596
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies)
Category: Circuit Design
Keyword: 
high speedlow powerfixed point DSP160 MHz0.18 µm
 Summary | Full Text:PDF(1.7MB)

Diagnosing Crosstalk Faults in Sequential Circuits Using Fault Simulation
Hiroshi TAKAHASHI Marong PHADOONGSIDHI Yoshinobu HIGAMI Kewal K. SALUJA Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10  pp. 1515-1525
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: Test and Diagnosis for Timing Faults
Keyword: 
diagnosiscrosstalk faultfault simulationsequential circuit
 Summary | Full Text:PDF(870.8KB)

Process Characterization and Optimization for a Novel Oxide-Free Insulated Gate Structure for InP MISFETs Having Silicon Interface Control Layer
Hiroshi TAKAHASHI Masatsugu YAMADA Yong-Gui XIE Seiya KASAI Hideki HASEGAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/10/01
Vol. E84-C  No. 10  pp. 1344-1349
Type of Manuscript:  Special Section PAPER (Joint Special Issue on Heterostructure Microelectronics with TWHM 2000 (Topical Workshop on Heterostructure Microelectronics 2000))
Category: Hetero-FETs & Their Integrated Circuits
Keyword: 
InPMISFETXPSC-V
 Summary | Full Text:PDF(1.2MB)

Fabrication and Characterization of InGaAs/InAlAs Insulated Gate Pseudomorphic HEMTs Having a Silicon Interface Control Layer
Yong-Gui XIE Seiya KASAI Hiroshi TAKAHASHI Chao JIANG Hideki HASEGAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/10/01
Vol. E84-C  No. 10  pp. 1335-1343
Type of Manuscript:  Special Section PAPER (Joint Special Issue on Heterostructure Microelectronics with TWHM 2000 (Topical Workshop on Heterostructure Microelectronics 2000))
Category: Hetero-FETs & Their Integrated Circuits
Keyword: 
insulated gatePHEMTInGaAsinterface controlFermi level pinning
 Summary | Full Text:PDF(793.9KB)

Design of C-Testable Modified-Booth Multipliers
Kwame Osei BOATENG Hiroshi TAKAHASHI Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2000/10/25
Vol. E83-D  No. 10  pp. 1868-1878
Type of Manuscript:  PAPER
Category: Fault Tolerance
Keyword: 
multipliermodified Booth Algorithmdesign for testability (DFT)C-testable design
 Summary | Full Text:PDF(873.5KB)

Hybrid External Cavity Lasers Composed of Spot-Size Converter Integrated LDs and UV Written Bragg Gratings in a Planar Lightwave Circuit on Si
Takuya TANAKA Hiroshi TAKAHASHI Yoshinori HIBINO Toshikazu HASHIMOTO Akira HIMENO Yasufumi YAMADA Yuichi TOHMORI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2000/06/25
Vol. E83-C  No. 6  pp. 875-883
Type of Manuscript:  Special Section PAPER (Special Issue on Advanced Optical Devices for Next Generation High-Speed Communication Systems and Photonic Networks)
Category: WDM Network Devices
Keyword: 
external cavity laserhybrid integrationgratingmultiwavelength laserPLC
 Summary | Full Text:PDF(1.3MB)

A 1.2 V, 30 MIPS, 0.3 mA/MIPS and 200 MIPS, 0.58 mA/MIPS Digital Signal Processors
Hiroshi TAKAHASHI Shintaro MIZUSHIMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2000/02/25
Vol. E83-C  No. 2  pp. 179-185
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Power High-Speed CMOS LSI Technologies)
Category: 
Keyword: 
high speedsuper low powerMIPSfixed point DSPpocket implantD flip-flopVIA-2 ROM1.2 V200 MIPS
 Summary | Full Text:PDF(2MB)

Diagnosing Delay Faults in Combinational Circuits Under the Ambiguous Delay Model
Kwame Osei BOATENG Hiroshi TAKAHASHI Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/12/25
Vol. E82-D  No. 12  pp. 1563-1571
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
combinational circuitambiguous delay modelmultiple fault diagnosispath-tracing method
 Summary | Full Text:PDF(659.1KB)

A Method of Generating Tests with Linearity Property for Gate Delay Faults in Combinational Circuits
Hiroshi TAKAHASHI Kwame Osei BOATENG Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/11/25
Vol. E82-D  No. 11  pp. 1466-1473
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
combinational circuitmarginal chipgate delay faulttest generationtest with linearity property
 Summary | Full Text:PDF(598KB)

Multiple Gate Delay Fault Diagnosis Using Test-Pairs for Marginal Delays
Kwame Osei BOATENG Hiroshi TAKAHASHI Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/07/25
Vol. E81-D  No. 7  pp. 706-715
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Diagnosis of VLSI)
Category: Fault Diagnosis
Keyword: 
combinational circuitfault diagnosismultiple delay faultdiagnostic rulespath-tracing methodtest-pairs for marginal delays
 Summary | Full Text:PDF(814.1KB)

A 100 MIPS High Speed and Low Power Digital Signal Processor
Hiroshi TAKAHASHI Shigeshi ABIKO Shintaro MIZUSHIMA Yuji OZAWA Kenichi TASHIRO Shigetoshi MURAMATSU Masahiro FUSUMADA Akemi TODOROKI Youichi TANAKA Masayasu ITOIGAWA Isao MORIOKA Hiroyuki MIZUNO Miki KOJIMA Giovanni NASO Emmanuel EGO Frank CHIRAT 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/12/25
Vol. E80-C  No. 12  pp. 1546-1552
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Power and High-Speed LSI Technologies)
Category: 
Keyword: 
100 MIPSdigital signal processinghigh speedlow powerCPU
 Summary | Full Text:PDF(750.2KB)

A Method of Multiple Fault Diagnosis in Sequential Circuits by Sensitizing Sequence Pairs
Nobuhiro YANAGIDA Hiroshi TAKAHASHI Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/01/25
Vol. E80-D  No. 1  pp. 28-37
Type of Manuscript:  Special Section PAPER (Special Issue on Fault-Tolerant Computing)
Category: Testing/Checking
Keyword: 
sequential circuitscircuit level diagnosissensitizing sequence pairsdeduction algorithmsuspected/candidate faults
 Summary | Full Text:PDF(760.6KB)

A Circuit Library for Low Power and High Speed Digital Signal Processor
Hiroshi TAKAHASHI Shigeshi ABIKO Shintaro MIZUSHIMA Yuni OZAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/12/25
Vol. E78-C  No. 12  pp. 1717-1725
Type of Manuscript:  Special Section PAPER (Special Issue on Low-power Analog, Digital LSIs and ASICs for Multimedia)
Category: 
Keyword: 
low powerhigh speedlow costGSMPDCNADCdigital signal processingpersonal communication50 MIPSCPU
 Summary | Full Text:PDF(903.7KB)

A Study for Testability of Redundant Faults in Combinational Circuits Using Delay Effects
Xiangqiu YU Hiroshi TAKAHASHI Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/07/25
Vol. E78-D  No. 7  pp. 822-829
Type of Manuscript:  Special Section PAPER (Special Issue on Verification, Test and Diagnosis of VLSI Systems)
Category: 
Keyword: 
test generationcombinational circuitsredundant faultsdelay effectextended seven-valued calculus
 Summary | Full Text:PDF(657.2KB)

Improved Forward Test Generation of Sequential Circuits Using Variable-Length Time Frames
Yuzo TAKAMATSU Taijiro OGAWA Hiroshi TAKAHASHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/07/25
Vol. E76-D  No. 7  pp. 832-836
Type of Manuscript:  Special Section LETTER (Special Issue on VLSI Testing and Testable Design)
Category: 
Keyword: 
forward test generationsequential circuitsvariable-length time framesstate escaping
 Summary | Full Text:PDF(333.1KB)

A Method of Generating Tests for Combinational Circuits with Multiple Faults
Hiroshi TAKAHASHI Nobukage IUCHI Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1992/07/25
Vol. E75-D  No. 4  pp. 569-576
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
multiple faultscombinational circuitstest generationrobust tests
 Summary | Full Text:PDF(641KB)

Fluorine Doping Levels in the Low-Pressure PCVD Process
Ryoji SETAKA Hiroshi TAKAHASHI 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1984/06/25
Vol. E67-E  No. 6  pp. 333-334
Type of Manuscript:  LETTER
Category: Optical and Quantum Electronics
Keyword: 
 Summary | Full Text:PDF(115.6KB)