Hiroshi NAKAMURA


A Runtime Optimization Selection Framework to Realize Energy Efficient Networks-on-Chip
Yuan HE Masaaki KONDO Takashi NAKADA Hiroshi SASAKI Shinobu MIWA Hiroshi NAKAMURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/12/01
Vol. E99-D  No. 12  pp. 2881-2890
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: Architecture
Keyword: 
Networks-on-Chipperformanceenergy efficiencyoptimizationselection
 Summary | Full Text:PDF(1.7MB)

An Operating System Guided Fine-Grained Power Gating Control Based on Runtime Characteristics of Applications
Atsushi KOSHIBA Mikiko SATO Kimiyoshi USAMI Hideharu AMANO Ryuichi SAKAMOTO Masaaki KONDO Hiroshi NAKAMURA Mitaro NAMIKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2016/08/01
Vol. E99-C  No. 8  pp. 926-935
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power and High-Speed Chips)
Category: 
Keyword: 
energy conservationpower gatingoperating systemmicroprocessor
 Summary | Full Text:PDF(2.7MB)

A Fine-Grained Power Gating Control on Linux Monitoring Power Consumption of Processor Functional Units
Atsushi KOSHIBA Motoki WADA Ryuichi SAKAMOTO Mikiko SATO Tsubasa KOSAKA Kimiyoshi USAMI Hideharu AMANO Masaaki KONDO Hiroshi NAKAMURA Mitaro NAMIKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2015/07/01
Vol. E98-C  No. 7  pp. 559-568
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power and High-Speed Chips)
Category: 
Keyword: 
energy conservationpower gatingoperating systemLinux
 Summary | Full Text:PDF(2.1MB)

Area-Efficient Microarchitecture for Reinforcement of Turbo Mode
Shinobu MIWA Takara INOUE Hiroshi NAKAMURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/05/01
Vol. E97-D  No. 5  pp. 1196-1210
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
microprocessorsturbo modechip temperaturedesign methodology
 Summary | Full Text:PDF(2.8MB)

Fine-Grained Run-Tume Power Gating through Co-optimization of Circuit, Architecture, and System Software Design
Hiroshi NAKAMURA Weihan WANG Yuya OHTA Kimiyoshi USAMI Hideharu AMANO Masaaki KONDO Mitaro NAMIKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/04/01
Vol. E96-C  No. 4  pp. 404-412
Type of Manuscript:  INVITED PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
low-power circuit techniquesfine grained power-gatingcompilersystem hierarchy cooperation
 Summary | Full Text:PDF(3.1MB)

Evaluation of a New Power-Gating Scheme Utilizing Data Retentiveness on Caches
Kyundong KIM Seidai TAKEDA Shinobu MIWA Hiroshi NAKAMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A  No. 12  pp. 2301-2308
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
low-powercacheleakage power
 Summary | Full Text:PDF(1.6MB)

Sleep Transistor Sizing Method Using Accurate Delay Estimation Considering Input Vector Pattern and Non-linear Current Model
Seidai TAKEDA Kyundong KIM Hiroshi NAKAMURA Kimiyoshi USAMI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12  pp. 2499-2509
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword: 
power gatingMTCMOSdelayleakage power
 Summary | Full Text:PDF(2MB)

Design Method of High Performance and Low Power Functional Units Considering Delay Variations
Kouichi WATANABE Masashi IMAI Masaaki KONDO Hiroshi NAKAMURA Takashi NANYA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12  pp. 3519-3528
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Circuit Synthesis
Keyword: 
delay variationdual-rail asynchronous circuitfunctional unitunflip-bit control
 Summary | Full Text:PDF(1.1MB)

Synthesis of Serial Local Clock Controllers for Asynchronous Circuit Design
Nattha SRETASEREEKUL Hiroshi SAITO Euiseok KIM Metehan OZCAN Masashi IMAI Hiroshi NAKAMURA Takashi NANYA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12  pp. 3028-3037
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: IP Design
Keyword: 
asynchronous controllerslogic synthesisControl Data Flow Graphs (CDFGs)Signal Transition Graphs (STGs)
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Evaluation of Checkpointing Mechanism on SCore Cluster System
Masaaki KONDO Takuro HAYASHIDA Masashi IMAI Hiroshi NAKAMURA Takashi NANYA Atsushi HORI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/12/01
Vol. E86-D  No. 12  pp. 2553-2562
Type of Manuscript:  Special Section PAPER (Special Issue on Dependable Computing)
Category: Dependable Software
Keyword: 
checkpointingrollback-recoverycluster systemhigh availability
 Summary | Full Text:PDF(648.7KB)

Reducing Memory System Energy by Software-Controlled On-Chip Memory
Masaaki KONDO Hiroshi NAKAMURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/04/01
Vol. E86-C  No. 4  pp. 580-588
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies)
Category: Architecture and Algorithms
Keyword: 
processor architecturecacheon-chip memoryway activationmemory traffic
 Summary | Full Text:PDF(886.6KB)

A Cascade ALU Architecture for Asynchronous Super-Scalar Processors
Motokazu OZAWA Masashi IMAI Yoichiro UENO Hiroshi NAKAMURA Takashi NANYA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/02/01
Vol. E84-C  No. 2  pp. 229-237
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Power High-Performance VLSI Processors and Technologies)
Category: 
Keyword: 
asynchronoussuperscalar processorcascade ALUfine grain pipeline
 Summary | Full Text:PDF(1.6MB)

A Double-Leve1-Vth Select Gate Array Architecture for Multilevel NAND Flash Memories
Ken TAKEUCHI Tomoharu TANAKA Hiroshi NAKAMURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/07/25
Vol. E79-C  No. 7  pp. 1013-1020
Type of Manuscript:  Special Section PAPER (Special Issue on the 1995 Symposium on VLSI Circuits (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.31, No.4 April 1996))
Category: Memory
Keyword: 
 Summary | Full Text:PDF(637.2KB)

A Novel Sensing Scheme with On-Chip Page Copy for Flexible Voltage NAND Flash Memories
Hiroshi NAKAMURA Jun-ichi MIYAMOTO Ken-ichi IMAMIYA Yoshihisa IWATA Yoshihisa SUGIURA Hideko OODAIRA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/06/25
Vol. E79-C  No. 6  pp. 836-844
Type of Manuscript:  Special Section PAPER (Special Issue on ULSI Memory Technology)
Category: Nonvolatile memories
Keyword: 
flash memorysense amplifierbit-by-bit program verifycapacitive couplingpage copy
 Summary | Full Text:PDF(853.9KB)

Mobile Service Control Point for Intelligent and Multimedia Mobile Communications
Hiroshi NAKAMURA Kenichi KIMURA Akihisa NAKAJIMA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 1994/09/25
Vol. E77-B  No. 9  pp. 1089-1095
Type of Manuscript:  Special Section PAPER (Special Issue on Mobile Multimedia Communications)
Category: 
Keyword: 
communication networks and servicesswitching and communication processingcommunication software
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FOREWORD
Kenkichi HIRADE Hiroshi SUZUKI Hideichi SASAOKA Hiroshi NAKAMURA Yukitsuna FURUYA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 1994/05/25
Vol. E77-B  No. 5  pp. 533-534
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF(188.3KB)

Voice Communication Connection Control in Digital Public Land Mobile Networks
Masami YABUSAKI Kouji YAMAMOTO Shinji UEBAYASHI Hiroshi NAKAMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/12/25
Vol. E75-A  No. 12  pp. 1702-1709
Type of Manuscript:  Special Section PAPER (Special Section on Networks and Mobile Communications)
Category: 
Keyword: 
digital public land mobile networkCODECTDMAchannel reassignment
 Summary | Full Text:PDF(660.1KB)

Power Efficient High-Level Modulation for High-Capacity Digital Radio Systems
Hiroshi NAKAMURA Yoshimasa DAIDO 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1989/05/25
Vol. E72-E  No. 5  pp. 633-640
Type of Manuscript:  PAPER
Category: Radio Communication
Keyword: 
 Summary | Full Text:PDF(572.4KB)

A New 90 MBPS 68 APSK Modem with Honeycomb Constellation for Digital Radio Relay Systems
Hiroshi NAKAMURA Noboru IIZUKA Eisuke FUKUDA Morihiko MINOWA Yoshimasa DAIDO Sadao TAKENAKA 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1988/06/25
Vol. E71-E  No. 6  pp. 591-599
Type of Manuscript:  PAPER
Category: Radio Communication
Keyword: 
 Summary | Full Text:PDF(697.7KB)

A 256 QAM Digital Radio System with a Low Rolloff Factor of 20% for Attaining 6.75 bps/Hz
Hiroshi NAKAMURA Eisuke FUKUDA Noburu IIZUKA Yoshimasa DAIDO Sadao TAKENAKA 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1988/01/25
Vol. E71-E  No. 1  pp. 43-50
Type of Manuscript:  PAPER
Category: Radio Communication
Keyword: 
 Summary | Full Text:PDF(761.5KB)

Power Penalty of Multilevel QAM Modem Caused by Two Simultaneously Existing lmpairments
Yoshimasa DAIDO Sadao TAKENAKA Hiroshi NAKAMURA 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1987/07/25
Vol. E70-E  No. 7  pp. 628-633
Type of Manuscript:  PAPER
Category: Radio Wave and Satellite Communication
Keyword: 
 Summary | Full Text:PDF(477.5KB)