Hiroshi MAKINO


A Large-Scale, Flip-Flop RAM Imitating a Logic LSI for Fast Development of Process Technology
Masako FUJII  Koji NII  Hiroshi MAKINO  Shigeki OHBAYASHI  Motoshige IGARASHI  Takeshi KAWAMURA  Miho YOKOTA  Nobuhiro TSUDA  Tomoaki YOSHIZAWA  Toshikazu TSUTSUI  Naohiko TAKESHITA  Naofumi MURATA  Tomohiro TANAKA  Takanari FUJIWARA  Kyoko ASAHINA  Masakazu OKADA  Kazuo TOMITA  Masahiko TAKEUCHI  Shigehisa YAMAMOTO  Hiromitsu SUGIMOTO  Hirofumi SHINOHARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/08/01
Vol. E91-C  No. 8  pp. 1338-1347
Type of Manuscript: Special Section PAPER (Special Section on Microelectronic Test Structures (ICMTS2007))
Category: 
Keyword: 
large-scale integrationlogic circuit fault diagnosisSRAMyield optimization
  Summary |  Full Text:PDF (1.7MB)

A Wide Range 1.0-3.6 V 200 Mbps, Push-Pull Output Buffer Using Parasitic Bipolar Transistors
Takahiro SHIMADA  Hiromi NOTANI  Yasunobu NAKASE  Hiroshi MAKINO  Shuhei IWADE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/04/01
Vol. E87-C  No. 4  pp. 571-577
Type of Manuscript: Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)
Category: 
Keyword: 
low power consumptionI/Oparasitic bipolar transistorforward biasdriverlevel converter
  Summary |  Full Text:PDF (739.9KB)

A Low-Power Microcontroller with Body-Tied SOI Technology
Hisakazu SATO  Yasuhiro NUNOMURA  Niichi ITOH  Koji NII  Kanako YOSHIDA  Hironobu ITO  Jingo NAKANISHI  Hidehiro TAKATA  Yasunobu NAKASE  Hiroshi MAKINO  Akira YAMADA  Takahiko ARAKAWA  Toru SHIMIZU  Yuichi HIRANO  Takashi IPPOSHI  Shuhei IWADE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/04/01
Vol. E87-C  No. 4  pp. 563-570
Type of Manuscript: Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)
Category: 
Keyword: 
low powerhigh speedmicrocontrollerSOI
  Summary |  Full Text:PDF (1.3MB)

A Low Standby Current DSP Core Using Improved ABC-MT-CMOS with Charge Pump Circuit
Hiromi NOTANI  Masayuki KOYAMA  Ryuji MANO  Hiroshi MAKINO  Yoshio MATSUDA  Osamu TOMISAWA  Shuhei IWADE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/04/01
Vol. E86-C  No. 4  pp. 597-603
Type of Manuscript: Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies)
Category: Circuit Design
Keyword: 
low powerstandby currentbackgate controlMT-CMOS
  Summary |  Full Text:PDF (832.4KB)

Signal Integrity Design and Analysis for a 400 MHz RISC Microcontroller
Akira YAMADA  Yasuhiro NUNOMURA  Hiroaki SUZUKI  Hisakazu SATO  Niichi ITOH  Tetsuya KAGEMOTO  Hironobu ITO  Takashi KURAFUJI  Nobuharu YOSHIOKA  Jingo NAKANISHI  Hiromi NOTANI  Rei AKIYAMA  Atsushi IWABU  Tadao YAMANAKA  Hidehiro TAKATA  Takeshi SHIBAGAKI  Takahiko ARAKAWA  Hiroshi MAKINO  Osamu TOMISAWA  Shuhei IWADE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/04/01
Vol. E86-C  No. 4  pp. 635-642
Type of Manuscript: Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies)
Category: Design Methods and Implementation
Keyword: 
microcontrollerhigh-speedsignal integrityIR dropdesign technique
  Summary |  Full Text:PDF (1.9MB)

Realistic Scaling Scenario for Sub-100 nm Embedded SRAM Based on 3-Dimensional Interconnect Simulation
Yasumasa TSUKAMOTO  Tatsuya KUNIKIYO  Koji NII  Hiroshi MAKINO  Shuhei IWADE  Kiyoshi ISHIKAWA  Yasuo INOUE  Norihiko KOTANI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/03/01
Vol. E86-C  No. 3  pp. 439-446
Type of Manuscript: Special Section PAPER (Special Issue on the 2002 IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'02))
Category: 
Keyword: 
embedded SRAMscaling merit3-dimensional interconnect simulation50 and 70 nm technology nodes
  Summary |  Full Text:PDF (984.5KB)

Novel VLIW Code Compaction Method for a 3D Geometry Processor
Hiroaki SUZUKI  Hiroyuki KAWAI  Hiroshi MAKINO  Yoshio MATSUDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11  pp. 2885-2893
Type of Manuscript: PAPER
Category: Digital Signal Processing
Keyword: 
VLIWcode compactionASSP3D geometry processorcomputer graphics
  Summary |  Full Text:PDF (1.5MB)

A Floating-Point Divider Using Redundant Binary Circuits and an Asynchronous Clock Scheme
Hiroaki SUZUKI  Hiroshi MAKINO  Koichiro MASHIKO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/01/20
Vol. E82-C  No. 1  pp. 105-110
Type of Manuscript: PAPER
Category: Electronic Circuits
Keyword: 
dividerfloating-point executionredundant binary circuitsasynchronous circuitself-timed circuit
  Summary |  Full Text:PDF (386.2KB)

A 286 MHz 64-b Floating Point Multiplier with Enhanced CG Operation
Hiroshi MAKINO  Hiroaki SUZUKI  Hiroyuki MORINAKA  Yasunobu NAKASE  Koichiro MASHIKO  Tadashi SUMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/07/20
Vol. E79-C  No. 7  pp. 915-924
Type of Manuscript: Special Section PAPER (Special Issue on the 1995 Symposium on VLSI Circuits (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.31, No.4 April 1996))
Category: Logic
Keyword: 
  Summary |  Full Text:PDF (935.7KB)

A 2.6-ns 64-b Fast and Small CMOS Adder
Hiroyuki MORINAKA  Hiroshi MAKINO  Yasunobu NAKASE  Hiroaki SUZUKI  Koichiro MASHIKO  Tadashi SUMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/04/20
Vol. E79-C  No. 4  pp. 530-537
Type of Manuscript: Special Section PAPER (Special Issue on Ultra-High-Speed LSIs)
Category: 
Keyword: 
additioncarry look-ahead adderbinary look-ahead addercarry selectmodified carry selectCMOSVLSI
  Summary |  Full Text:PDF (644.2KB)

A Design of High-Speed 4-2 Compressor for Fast Multiplier
Hiroshi MAKINO  Hiroaki SUZUKI  Hiroyuki MORINAKA  Yasunobu NAKASE  Hirofumi SHINOHARA  Koichiro MASHIKO  Tadashi SUMI  Yasutaka HORIBA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/04/20
Vol. E79-C  No. 4  pp. 538-548
Type of Manuscript: Special Section PAPER (Special Issue on Ultra-High-Speed LSIs)
Category: 
Keyword: 
4-2 compressormultiplierredundant binarytransmission gateCMOS circuit
  Summary |  Full Text:PDF (1015.1KB)

An Application of Air-Bridge Metal Interconnections to High Speed GaAs LSI's
Minoru NODA  Hiroshi MATSUOKA  Norio HIGASHISAKA  Masaaki SHIMADA  Hiroshi MAKINO  Shuichi MATSUE  Yasuo MITSUI  Kazuo NISHITANI  Akiharu TADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1992/10/20
Vol. E75-C  No. 10  pp. 1146-1153
Type of Manuscript: Special Section PAPER (Special Issue on Compound Semiconductor Integrated Circuits)
Category: 
Keyword: 
air-bridgeinterconnectionpropagation delay timeGaAs LSI
  Summary |  Full Text:PDF (1.2MB)