Hiroshi IWATA


Formal Verification-Based Redundancy Identification of Transition Faults with Broadside Scan Tests
Hiroshi IWATA Nanami KATAYAMA Ken'ichi YAMAGUCHI 
Publication:   
Publication Date: 2017/06/01
Vol. E100-D  No. 6  pp. 1182-1189
Type of Manuscript:  Special Section PAPER (Special Section on Formal Approach)
Category: Formal techniques
Keyword: 
redundancy identificationtransition faultsbroadside scan testformal verification and functional equivalence
 Summary | Full Text:PDF(651.8KB)

A Method of Path Mapping from RTL to Gate Level and Its Application to False Path Identification
Hiroshi IWATA Satoshi OHTAKE Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/07/01
Vol. E93-D  No. 7  pp. 1857-1865
Type of Manuscript:  PAPER
Category: Information Network
Keyword: 
false pathhigh level testingpath mappingfunctional equivalence
 Summary | Full Text:PDF(348.9KB)