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Hiroshi INOKAWA

Effect of Arrangement of Input Gates on Logic Switching Characteristics of Nanodot Array Device Mingu JO Yuki KATO Masashi ARITA Yukinori ONO Akira FUJIWARA Hiroshi INOKAWA Yasuo TAKAHASHI Jung-Bum CHOI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/05/01 Vol. E95-C No. 5 pp. 865-870 Type of Manuscript: Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices) Category: Keyword: single electron, nanodot, logic gate, dot array, Coulomb blockade,
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Transfer and Detection of Single Electrons Using Metal-Oxide-Semiconductor Field-Effect Transistors Wancheng ZHANG Katsuhiko NISHIGUCHI Yukinori ONO Akira FUJIWARA Hiroshi YAMAGUCHI Hiroshi INOKAWA Yasuo TAKAHASHI Nan-Jian WU
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/05/01 Vol. E90-C No. 5 pp. 943-948 Type of Manuscript: Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices) Category: Emerging Devices Keyword: single-electron, MOSFET, turnstile, single-electron detection,
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Multifunctional Boolean Logic Using Single-Electron Transistors Katsuhiko NISHIGUCHI Hiroshi INOKAWA Yukinori ONO Akira FUJIWARA Yasuo TAKAHASHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/11/01 Vol. E87-C No. 11 pp. 1809-1817 Type of Manuscript: Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics) Category: Keyword: single-electron transistor, programmable Boolean logic, silicon-on-insulator,
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A Simulation Methodology for Single-Electron Multiple-Valued Logics and Its Application to a Latched Parallel Counter Hiroshi INOKAWA Yasuo TAKAHASHI Katsuhiko DEGAWA Takafumi AOKI Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/11/01 Vol. E87-C No. 11 pp. 1818-1826 Type of Manuscript: Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics) Category: Keyword: single-electron transistor (SET), multiple-valued logic (MVL), counter, analytical model, SPICE,
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A Single-Electron-Transistor Logic Gate Family for Binary, Multiple-Valued and Mixed-Mode Logic Katsuhiko DEGAWA Takafumi AOKI Tatsuo HIGUCHI Hiroshi INOKAWA Yasuo TAKAHASHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/11/01 Vol. E87-C No. 11 pp. 1827-1836 Type of Manuscript: Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics) Category: Keyword: single-electron transistors, multiple-valued logic, quantum devices, logic circuits, parallel counters,
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Megabit-Class Size-Configurable 250-MHz SRAM Macrocells with a Squashed-Memory-Cell Architecture Nobutaro SHIBATA Hiroshi INOKAWA Keiichiro TOKUNAGA Soichi OHTA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/01/20 Vol. E82-C No. 1 pp. 94-104 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: SRAM, macrocell, size-configurable, high speed, low power, per-bitline architecture, current-sense amplifier, squashed memory cell, trench isolation,
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