Hiroshi INOKAWA


Effect of Arrangement of Input Gates on Logic Switching Characteristics of Nanodot Array Device
Mingu JO Yuki KATO Masashi ARITA Yukinori ONO Akira FUJIWARA Hiroshi INOKAWA Yasuo TAKAHASHI Jung-Bum CHOI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/05/01
Vol. E95-C  No. 5  pp. 865-870
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: 
Keyword: 
single electronnanodotlogic gatedot arrayCoulomb blockade
 Summary | Full Text:PDF(2.6MB)

Transfer and Detection of Single Electrons Using Metal-Oxide-Semiconductor Field-Effect Transistors
Wancheng ZHANG Katsuhiko NISHIGUCHI Yukinori ONO Akira FUJIWARA Hiroshi YAMAGUCHI Hiroshi INOKAWA Yasuo TAKAHASHI Nan-Jian WU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/05/01
Vol. E90-C  No. 5  pp. 943-948
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: Emerging Devices
Keyword: 
single-electronMOSFETturnstilesingle-electron detection
 Summary | Full Text:PDF(789.8KB)

Multifunctional Boolean Logic Using Single-Electron Transistors
Katsuhiko NISHIGUCHI Hiroshi INOKAWA Yukinori ONO Akira FUJIWARA Yasuo TAKAHASHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/11/01
Vol. E87-C  No. 11  pp. 1809-1817
Type of Manuscript:  Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics)
Category: 
Keyword: 
single-electron transistorprogrammable Boolean logicsilicon-on-insulator
 Summary | Full Text:PDF(1.5MB)

A Simulation Methodology for Single-Electron Multiple-Valued Logics and Its Application to a Latched Parallel Counter
Hiroshi INOKAWA Yasuo TAKAHASHI Katsuhiko DEGAWA Takafumi AOKI Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/11/01
Vol. E87-C  No. 11  pp. 1818-1826
Type of Manuscript:  Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics)
Category: 
Keyword: 
single-electron transistor (SET)multiple-valued logic (MVL)counteranalytical modelSPICE
 Summary | Full Text:PDF(646.3KB)

A Single-Electron-Transistor Logic Gate Family for Binary, Multiple-Valued and Mixed-Mode Logic
Katsuhiko DEGAWA Takafumi AOKI Tatsuo HIGUCHI Hiroshi INOKAWA Yasuo TAKAHASHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/11/01
Vol. E87-C  No. 11  pp. 1827-1836
Type of Manuscript:  Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics)
Category: 
Keyword: 
single-electron transistorsmultiple-valued logicquantum deviceslogic circuitsparallel counters
 Summary | Full Text:PDF(1.1MB)

Megabit-Class Size-Configurable 250-MHz SRAM Macrocells with a Squashed-Memory-Cell Architecture
Nobutaro SHIBATA Hiroshi INOKAWA Keiichiro TOKUNAGA Soichi OHTA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/01/25
Vol. E82-C  No. 1  pp. 94-104
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
SRAMmacrocellsize-configurablehigh speedlow powerper-bitline architecturecurrent-sense amplifiersquashed memory celltrench isolation
 Summary | Full Text:PDF(931.1KB)