IEICE SEARCH SYSTEM

Hiromi HIRAISHI

Symbolic Model Checking of Deadlock Free Property of Task Control Architecture Hiromi HIRAISHI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2002/10/01 Vol. E85-D No. 10 pp. 1579-1586 Type of Manuscript: Special Section PAPER (Special Issue on Test and Verification of VLSI) Category: Verification Keyword: verification, symbolic model checking, deadlock, robot control program, concurrent process,
	Summary \| Full Text:PDF (267.5KB)

FOREWORD Hiromi HIRAISHI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2002/10/01 Vol. E85-D No. 10 pp. 1465-1465 Type of Manuscript: FOREWORD Category: Keyword:
	Summary \| Full Text:PDF (126.5KB)

Formal Verification of Totally Self-Checking Properties of Combinational Circuits Kazuo KAWAKUBO Koji TANAKA Hiromi HIRAISHI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1997/01/20 Vol. E80-D No. 1 pp. 57-62 Type of Manuscript: Special Section PAPER (Special Issue on Fault-Tolerant Computing) Category: Verification Keyword: formal verification, totally self-checking, fault tolerance, binary decision diagram,
	Summary \| Full Text:PDF (509.3KB)

Towards Verification of Bit-Slice Circuits--Time-Space Modal Model Checking Approach-- Hiromi HIRAISHI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1995/07/20 Vol. E78-D No. 7 pp. 791-795 Type of Manuscript: Special Section PAPER (Special Issue on Verification, Test and Diagnosis of VLSI Systems) Category: Keyword: formal verification, time-space modal logic, symbolic model checking, logic design verification, verification of bit-slice circuits,
	Summary \| Full Text:PDF (391.7KB)

Temporal Verification of Real-Time Systems Sérgio V. CAMPOS Edmund M. CLARKE Wilfredo MARRERO Marius MINEA Hiromi HIRAISHI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1995/07/20 Vol. E78-D No. 7 pp. 796-801 Type of Manuscript: Special Section PAPER (Special Issue on Verification, Test and Diagnosis of VLSI Systems) Category: Keyword: formal verification, real-time system, temporal logic,
	Summary \| Full Text:PDF (634.3KB)

An Application of Regular Temporal Logic to Verification of Fail-Safeness of a Comparator for Redundant System Kazuo KAWAKUBO Hiromi HIRAISHI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/07/20 Vol. E76-D No. 7 pp. 763-770 Type of Manuscript: Special Section PAPER (Special Issue on VLSI Testing and Testable Design) Category: Keyword: fail-safe, fault tolerance, formal verification, temporal logic,
	Summary \| Full Text:PDF (718.5KB)

Formal Design Verification of Sequential Machines Based on Symbolic Model Checking for Branching Time Regular Temporal Logic Kiyoharu HAMAGUCHI Hiromi HIRAISHI Shuzo YAJIMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1992/10/20 Vol. E75-A No. 10 pp. 1220-1229 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: design verification, sequential machines, temporal logic, model checking, binary decision diagram,
	Summary \| Full Text:PDF (787.7KB)