Hiromi HIRAISHI


FOREWORD
Hiromi HIRAISHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10  pp. 1465-1465
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
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Symbolic Model Checking of Deadlock Free Property of Task Control Architecture
Hiromi HIRAISHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10  pp. 1579-1586
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: Verification
Keyword: 
verificationsymbolic model checkingdeadlockrobot control programconcurrent process
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Formal Verification of Totally Self-Checking Properties of Combinational Circuits
Kazuo KAWAKUBO Koji TANAKA Hiromi HIRAISHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/01/25
Vol. E80-D  No. 1  pp. 57-62
Type of Manuscript:  Special Section PAPER (Special Issue on Fault-Tolerant Computing)
Category: Verification
Keyword: 
formal verificationtotally self-checkingfault tolerancebinary decision diagram
 Summary | Full Text:PDF(508.2KB)

Towards Verification of Bit-Slice Circuits--Time-Space Modal Model Checking Approach--
Hiromi HIRAISHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/07/25
Vol. E78-D  No. 7  pp. 791-795
Type of Manuscript:  Special Section PAPER (Special Issue on Verification, Test and Diagnosis of VLSI Systems)
Category: 
Keyword: 
formal verificationtime-space modal logicsymbolic model checkinglogic design verificationverification of bit-slice circuits
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Temporal Verification of Real-Time Systems
Sérgio V. CAMPOS Edmund M. CLARKE Wilfredo MARRERO Marius MINEA Hiromi HIRAISHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/07/25
Vol. E78-D  No. 7  pp. 796-801
Type of Manuscript:  Special Section PAPER (Special Issue on Verification, Test and Diagnosis of VLSI Systems)
Category: 
Keyword: 
formal verificationreal-time systemtemporal logic
 Summary | Full Text:PDF(633KB)

An Application of Regular Temporal Logic to Verification of Fail-Safeness of a Comparator for Redundant System
Kazuo KAWAKUBO Hiromi HIRAISHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/07/25
Vol. E76-D  No. 7  pp. 763-770
Type of Manuscript:  Special Section PAPER (Special Issue on VLSI Testing and Testable Design)
Category: 
Keyword: 
fail-safefault toleranceformal verificationtemporal logic
 Summary | Full Text:PDF(717.1KB)

Formal Design Verification of Sequential Machines Based on Symbolic Model Checking for Branching Time Regular Temporal Logic
Kiyoharu HAMAGUCHI Hiromi HIRAISHI Shuzo YAJIMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/10/25
Vol. E75-A  No. 10  pp. 1220-1229
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
design verificationsequential machinestemporal logicmodel checkingbinary decision diagram
 Summary | Full Text:PDF(786KB)