Hiroki SAKURAI


A Digitally Assisted Gain and Offset Error Cancellation Technique for a CMOS Pipelined ADC with a 1.5-bit Bit-Block Architecture
Hiroki SAKURAI Shigeto TANAKA Yasuhiro SUGIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/10/01
Vol. E90-A  No. 10  pp. 2272-2279
Type of Manuscript:  PAPER
Category: Analog Signal Processing
Keyword: 
capacitor mismatchCMOS pipelined ADC1.5-bit bit-blocksaveraging in digital domainOversampling ADC
 Summary | Full Text:PDF(601.7KB)

The Realization of an Area-Efficient CMOS Bandgap Reference Circuit with Less than 1.25 V of Output Voltage Using a Fractional VBE Amplification Scheme
Hiroki SAKURAI Yasuhiro SUGIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/02/01
Vol. E90-C  No. 2  pp. 499-506
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
voltage referencelow reference voltagesmall diode areaVBE amplificationCMOS
 Summary | Full Text:PDF(368.1KB)

Analysis and Design of a Current-Mode PWM Buck Converter Adopting the Output-Voltage Independent Second-Order Slope Compensation Scheme
Hiroki SAKURAI Yasuhiro SUGIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/02/01
Vol. E88-A  No. 2  pp. 490-497
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
PWM buck convertercurrent-mode controlslope compensation
 Summary | Full Text:PDF(361KB)

The Design of a 2.7 V, 200 MS/s, and 14-Bit CMOS D/A Converter with 63 dB of SFDR Characteristics for the 90 MHz Output Signal
Hiroki SAKURAI Yasuhiro SUGIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/06/01
Vol. E86-C  No. 6  pp. 1077-1084
Type of Manuscript:  Special Section PAPER (Special Issue on Devices and Circuits for Next Generation Multi-Media Communication Systems)
Category: 
Keyword: 
high-speed DAClow-voltage DAChigh-resolution DACCMOS DACSFDR characteristics
 Summary | Full Text:PDF(616.9KB)

A Half-Pel Precision Motion Estimation Processor for NTSC-Resolution Video
Shin-ichi URAMOTO Akihiko TAKABATAKE Mitsuyoshi SUZUKI Hiroki SAKURAI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/12/25
Vol. E77-C  No. 12  pp. 1930-1936
Type of Manuscript:  Special Section PAPER (Special Issue on Multimedia, Analog and Processing LSIs)
Category: Processors
Keyword: 
image compressionmotion estimationsystolic array
 Summary | Full Text:PDF(718.3KB)