Hiroki NAKAHARA


A Threshold Neuron Pruning for a Binarized Deep Neural Network on an FPGA
Tomoya FUJII Shimpei SATO Hiroki NAKAHARA 
Publication:   
Publication Date: 2018/02/01
Vol. E101-D  No. 2  pp. 376-386
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Emerging Applications
Keyword: 
machine learningdeep learningpruningFPGA
 Summary | Full Text:PDF(1.2MB)

An FPGA Realization of a Random Forest with k-Means Clustering Using a High-Level Synthesis Design
Akira JINGUJI Shimpei SATO Hiroki NAKAHARA 
Publication:   
Publication Date: 2018/02/01
Vol. E101-D  No. 2  pp. 354-362
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Emerging Applications
Keyword: 
machine learningrandom forestk-means clusteringFPGA
 Summary | Full Text:PDF(1.4MB)

A Memory-Based IPv6 Lookup Architecture Using Parallel Index Generation Units
Hiroki NAKAHARA Tsutomu SASAO Munehiro MATSUURA Hisashi IWAMOTO Yasuhiro TERAO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2015/02/01
Vol. E98-D  No. 2  pp. 262-271
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Architecture
Keyword: 
CAMIP lookupindex generation unitFPGA
 Summary | Full Text:PDF(1MB)

A Packet Classifier Based on Prefetching EVMDD (k) Machines
Hiroki NAKAHARA Tsutomu SASAO Munehiro MATSUURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/09/01
Vol. E97-D  No. 9  pp. 2243-2252
Type of Manuscript:  Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: Logic Design
Keyword: 
many corepacket classificationdecision diagrammulti-valued logic
 Summary | Full Text:PDF(2.1MB)

A Virus Scanning Engine Using an MPU and an IGU Based on Row-Shift Decomposition
Hiroki NAKAHARA Tsutomu SASAO Munehiro MATSUURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/08/01
Vol. E96-D  No. 8  pp. 1667-1675
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Application
Keyword: 
pattern matchingvirus scanningindex generation functionCAM
 Summary | Full Text:PDF(1.1MB)

A Design Method of a Regular Expression Matching Circuit Based on Decomposed Automaton
Hiroki NAKAHARA Tsutomu SASAO Munehiro MATSUURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/02/01
Vol. E95-D  No. 2  pp. 364-373
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Design Methodology
Keyword: 
regular expressionNFADFAMNFAUFPGA
 Summary | Full Text:PDF(780.2KB)

A Parallel Branching Program Machine for Sequential Circuits: Implementation and Evaluation
Hiroki NAKAHARA Tsutomu SASAO Munehiro MATSUURA Yoshifumi KAWAMURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/08/01
Vol. E93-D  No. 8  pp. 2048-2058
Type of Manuscript:  Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: Logic Design
Keyword: 
embedded systembranching program machinemulti-processingBDD
 Summary | Full Text:PDF(1MB)

A Quaternary Decision Diagram Machine: Optimization of Its Code
Tsutomu SASAO Hiroki NAKAHARA Munehiro MATSUURA Yoshifumi KAWAMURA Jon T. BUTLER 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/08/01
Vol. E93-D  No. 8  pp. 2026-2035
Type of Manuscript:  INVITED PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: 
Keyword: 
quarternary decision diagrambranching program machine
 Summary | Full Text:PDF(650.9KB)

A PC-Based Logic Simulator Using a Look-Up Table Cascade Emulator
Hiroki NAKAHARA Tsutomu SASAO Munehiro MATSUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12  pp. 3471-3481
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Simulation and Verification
Keyword: 
LUT cascadebdd_for_cffunctional decomposition
 Summary | Full Text:PDF(634KB)

A Design Algorithm for Sequential Circuits Using LUT Rings
Hiroki NAKAHARA Tsutomu SASAO Munehiro MATSUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12  pp. 3342-3350
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
reconfigurable architectureLUT cascadeBDD_for_CFfunctional decomposition
 Summary | Full Text:PDF(699.9KB)