Hirofumi NAKANO


A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation
Yohei NAKATA Yuta KIMI Shunsuke OKUMURA Jinwook JUNG Takuya SAWADA Taku TOSHIKAWA Makoto NAGATA Hirofumi NAKANO Makoto YABUUCHI Hidehiro FUJIWARA Koji NII Hiroyuki KAWAI Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2014/04/01
Vol. E97-C  No. 4  pp. 332-341
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design,---,Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
design for robustnesscachevariation tolerance7T/14T SRAM
 Summary | Full Text:PDF(4.6MB)

High Efficiency AlGaAs/GaAs Power HBTs at a Low Supply Voltage for Digital Cellular Phones
Teruyuki SHIMURA Takeshi MIURA Yutaka UNEME Hirofumi NAKANO Ryo HATTORI Mutsuyuki OTSUBO Kazutomi MORI Akira INOUE Noriyuki TANINO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/06/25
Vol. E80-C  No. 6  pp. 740-745
Type of Manuscript:  Special Section PAPER (Special Issue on Microwave and Millimeterwave High-power Devices)
Category: 
Keyword: 
heterojunction bipolar transistordigital cellular phoneindividual thermal shuntemitter air-bridgebias mode
 Summary | Full Text:PDF(588.7KB)