IEICE SEARCH SYSTEM

Hiroaki SUZUKI

Adaptive Supply Voltage for Low-Power Ripple-Carry and Carry-Select Adders Hiroaki SUZUKI Woopyo JEONG Kaushik ROY
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/04/01 Vol. E90-C No. 4 pp. 865-876 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: adaptive supply voltage, low power design, adders, CMOS digital integrated circuit,
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Comparing Software Rejuvenation Policies under Different Dependability Measures Tadashi DOHI Hiroaki SUZUKI Kishor S. TRIVEDI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2004/08/01 Vol. E87-D No. 8 pp. 2078-2085 Type of Manuscript: PAPER Category: Dependable Computing Keyword: software rejuvenation, software aging, system availability, mean up rate, preventive maintenance, numerical optimization, fault management, design diversity,
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Signal Integrity Design and Analysis for a 400 MHz RISC Microcontroller Akira YAMADA Yasuhiro NUNOMURA Hiroaki SUZUKI Hisakazu SATO Niichi ITOH Tetsuya KAGEMOTO Hironobu ITO Takashi KURAFUJI Nobuharu YOSHIOKA Jingo NAKANISHI Hiromi NOTANI Rei AKIYAMA Atsushi IWABU Tadao YAMANAKA Hidehiro TAKATA Takeshi SHIBAGAKI Takahiko ARAKAWA Hiroshi MAKINO Osamu TOMISAWA Shuhei IWADE
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2003/04/01 Vol. E86-C No. 4 pp. 635-642 Type of Manuscript: Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies) Category: Design Methods and Implementation Keyword: microcontroller, high-speed, signal integrity, IR drop, design technique,
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Cost-Effective Analysis of Software Systems with Periodic Rejuvenation Hiroaki SUZUKI Tadashi DOHI Hiroyuki OKAMURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/12/01 Vol. E85-A No. 12 pp. 2923-2932 Type of Manuscript: PAPER Category: Reliability, Maintainability and Safety Analysis Keyword: preventive maintenance, software rejuvenation, cost effectiveness, total time on test, non-parametric estimation,
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A Programmable Geometry Processor with Enhanced Four-Parallel SIMD Type Processing Core for PC-Based 3D Graphics Hiroyuki KAWAI Yoshitsugu INOUE Junko KOBARA Robert STREITENBERGER Hiroaki SUZUKI Hiroyasu NEGISHI Masatoshi KAMEYAMA Kazunari INOUE Yasutaka HORIBA Kazuyasu FUJISHIMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2002/05/01 Vol. E85-C No. 5 pp. 1200-1210 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: 3D graphics, programmable, geometry, SIMD, clip test,
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Novel VLIW Code Compaction Method for a 3D Geometry Processor Hiroaki SUZUKI Hiroyuki KAWAI Hiroshi MAKINO Yoshio MATSUDA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/11/01 Vol. E84-A No. 11 pp. 2885-2893 Type of Manuscript: PAPER Category: Digital Signal Processing Keyword: VLIW, code compaction, ASSP, 3D geometry processor, computer graphics,
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A Floating-Point Divider Using Redundant Binary Circuits and an Asynchronous Clock Scheme Hiroaki SUZUKI Hiroshi MAKINO Koichiro MASHIKO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/01/20 Vol. E82-C No. 1 pp. 105-110 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: divider, floating-point execution, redundant binary circuits, asynchronous circuit, self-timed circuit,
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A 286 MHz 64-b Floating Point Multiplier with Enhanced CG Operation Hiroshi MAKINO Hiroaki SUZUKI Hiroyuki MORINAKA Yasunobu NAKASE Koichiro MASHIKO Tadashi SUMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/07/20 Vol. E79-C No. 7 pp. 915-924 Type of Manuscript: Special Section PAPER (Special Issue on the 1995 Symposium on VLSI Circuits (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.31, No.4 April 1996)) Category: Logic Keyword:
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A Design of High-Speed 4-2 Compressor for Fast Multiplier Hiroshi MAKINO Hiroaki SUZUKI Hiroyuki MORINAKA Yasunobu NAKASE Hirofumi SHINOHARA Koichiro MASHIKO Tadashi SUMI Yasutaka HORIBA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/04/20 Vol. E79-C No. 4 pp. 538-548 Type of Manuscript: Special Section PAPER (Special Issue on Ultra-High-Speed LSIs) Category: Keyword: 4-2 compressor, multiplier, redundant binary, transmission gate, CMOS circuit,
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A 2.6-ns 64-b Fast and Small CMOS Adder Hiroyuki MORINAKA Hiroshi MAKINO Yasunobu NAKASE Hiroaki SUZUKI Koichiro MASHIKO Tadashi SUMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/04/20 Vol. E79-C No. 4 pp. 530-537 Type of Manuscript: Special Section PAPER (Special Issue on Ultra-High-Speed LSIs) Category: Keyword: addition, carry look-ahead adder, binary look-ahead adder, carry select, modified carry select, CMOS, VLSI,
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A 0.9-V, 2.5 MHz CMOS 32-bit Microprocessor Hiroaki SUZUKI Toshichika SAKAI Hisao HARIGAI Yoichi YANO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/04/20 Vol. E78-C No. 4 pp. 389-393 Type of Manuscript: Special Section PAPER (Special Issue on Low-Voltage, Low-Power Integrated Circuits) Category: Digital Circuits Keyword: RISC, microprocessor, CMOS LSI, low-power,
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Automated Bias Control (ABC) Circuit for High-Performance VLSI's Tadahiro KURODA Toshiyuki FUKUNAGA Kenji MATSUO Kazuhiko KASAI Ayako HIRATA Shinji FUJII Masahiro KIMURA Hiroaki SUZUKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1992/04/20 Vol. E75-C No. 4 pp. 539-546 Type of Manuscript: Special Section PAPER (Joint Special Issue on the 1991 VLSI Circuits Symposium) Category: Keyword:
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