Hiroaki NISHI


Novel Method to Watermark Anonymized Data for Data Publishing
Yuichi NAKAMURA Yoshimichi NAKATSUKA Hiroaki NISHI 
Publication:   
Publication Date: 2017/08/01
Vol. E100-D  No. 8  pp. 1671-1679
Type of Manuscript:  Special Section PAPER (Special Section on Information and Communication System Security)
Category: Privacy
Keyword: 
anonymizationdistortion attackturbo codewatermarking
 Summary | Full Text:PDF(1.1MB)

Time Synchronization Technique Using EPON for Next-Generation Power Grids
Yuichi NAKAMURA Andy HARVATH Hiroaki NISHI 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2016/04/01
Vol. E99-B  No. 4  pp. 859-866
Type of Manuscript:  Special Section PAPER (Special Section on Autonomous Decentralized Systems Technologies and Applications for Next-Generation Social Infrastructure)
Category: 
Keyword: 
power gridsmart gridtime synchronizationEthernet Passive Optical Network
 Summary | Full Text:PDF(2.6MB)

Self-Organized Link State Aware Routing for Multiple Mobile Agents in Wireless Network
Akihiro ODA Hiroaki NISHI 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2010/08/01
Vol. E93-B  No. 8  pp. 2012-2021
Type of Manuscript:  Special Section PAPER (Special Section on Implementation, Experiments, and Practice for Ad Hoc and Mesh Networks)
Category: 
Keyword: 
wireless sensor networkMANETsrouting algorithmQoS sensitive routingRSSI
 Summary | Full Text:PDF(1.3MB)

Cache-Based Network Processor Architecture: Evaluation with Real Network Traffic
Michitaka OKUNO Shinji NISHIMURA Shin-ichi ISHIDA Hiroaki NISHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/11/01
Vol. E89-C  No. 11  pp. 1620-1628
Type of Manuscript:  Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies)
Category: 
Keyword: 
100-Gbps Ethernetnetwork processorcachenetwork trafficlow power
 Summary | Full Text:PDF(1.7MB)

Design Philosophy of a Networking-Oriented Data-Driven Processor: CUE
Hiroaki NISHIKAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/03/01
Vol. E89-C  No. 3  pp. 221-229
Type of Manuscript:  INVITED PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era)
Category: 
Keyword: 
data-drivenmultiprocessingreal-timeVLSI
 Summary | Full Text:PDF(1021.9KB)

100-Gb/s Physical-Layer Architecture for Next-Generation Ethernet
Hidehiro TOYODA Shinji NISHIMURA Michitaka OKUNO Kouji FUKUDA Kouji NAKAHARA Hiroaki NISHI 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2006/03/01
Vol. E89-B  No. 3  pp. 696-703
Type of Manuscript:  Special Section PAPER (Special Section on the Next Generation Ethernet Technologies)
Category: 
Keyword: 
EthernetMANskewFEC
 Summary | Full Text:PDF(1.8MB)

Designing Coplanar Superconducting Lumped-Element Bandpass Filters Using a Mechanical Tuning Method
Shigeki HONTSU Kazuyuki AGEMURA Hiroaki NISHIKAWA Masanobu KUSUNOKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/02/01
Vol. E89-C  No. 2  pp. 151-155
Type of Manuscript:  Special Section PAPER (Special Section on Superconducting High-frequency Devices)
Category: 
Keyword: 
lumped-element bandpass filtercoplanar type circuitmechanical tuningsoftware-defined radio (SDR)
 Summary | Full Text:PDF(676KB)

Low-Power Network-Packet-Processing Architecture Using Process-Learning Cache for High-End Backbone Router
Michitaka OKUNO Shin-ichi ISHIDA Hiroaki NISHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/04/01
Vol. E88-C  No. 4  pp. 536-543
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP)
Category: Digital
Keyword: 
routerEthernetpacket-processing enginenetwork processorcache-based packet-processing engine
 Summary | Full Text:PDF(383.1KB)

SoC Architecture Synthesis Methodology Based on High-Level IPs
Michiaki MURAOKA Hiroaki NISHI Rafael K. MORIZAWA Hideaki YOKOTA Yoichi ONISHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12  pp. 3057-3067
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: System Level Design
Keyword: 
system level designarchitecture synthesishigh level IPCAD
 Summary | Full Text:PDF(3.7MB)

Signal Transmission and Coding Architecture for Next-Generation Ethernet
Hidehiro TOYODA Hiroaki NISHI Shinji NISHIMURA Hisaaki KANAI Katsuyoshi HARASAWA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/11/01
Vol. E86-D  No. 11  pp. 2317-2324
Type of Manuscript:  Special Section PAPER (Special Issue on New Technologies in the Internet and their Applications)
Category: 
Keyword: 
100-Gigabit Ethernet64B/66Bskew compensation
 Summary | Full Text:PDF(1.9MB)

Architecture and Evaluation of a Third-Generation RHiNET Switch for High-Performance Parallel Computing
Hiroaki NISHI Shinji NISHIMURA Katsuyoshi HARASAWA Tomohiro KUDOH Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/10/01
Vol. E86-D  No. 10  pp. 1987-1995
Type of Manuscript:  Special Section PAPER (Special Issue on Development of Advanced Computer Systems)
Category: 
Keyword: 
RHiNETcluster computing networkhigh-performance systemflow control
 Summary | Full Text:PDF(762.7KB)

A High-Speed, Highly-Reliable Network Switch for Parallel Computing System Using Optical Interconnection
Shinji NISHIMURA Tomohiro KUDOH Hiroaki NISHI Koji TASHO Katsuyoshi HARASAWA Shigeto AKUTSU Shuji FUKUDA Yasutaka SHIKICHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/03/01
Vol. E84-C  No. 3  pp. 288-294
Type of Manuscript:  Special Section PAPER (Special Issue on Optical Interconnects/Optical Signal Processing)
Category: Optical Interconnection Systems
Keyword: 
optical interconnectionparallel computingnetwork switchLANSAN
 Summary | Full Text:PDF(1.7MB)

Data-Driven Implementation of Highly Efficient TCP/IP Handler to Access the TINA Network
Hiroshi ISHII Hiroaki NISHIKAWA Yuji INOUE 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2000/06/25
Vol. E83-B  No. 6  pp. 1355-1362
Type of Manuscript:  PAPER
Category: Software Platform
Keyword: 
fault managementTINAdistributed processing environmentdata-driven processorpipeline processing schemeTCP/IP
 Summary | Full Text:PDF(383.8KB)

The RDT Router Chip: A Versatile Router for Supporting a Distributed Shared Memory
Hiroaki NISHI Ken-ichiro ANJO Tomohiro KUDOH Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/09/25
Vol. E80-D  No. 9  pp. 854-862
Type of Manuscript:  Special Section PAPER (Special Issue on Architectures, Algorithms and Networks for Massively Parallel Computing)
Category: Interconnection Networks
Keyword: 
routerinterconnection networkcache coherent distributed shared memory
 Summary | Full Text:PDF(794.5KB)

Data-Driven Fault Management for TINA Applications
Hiroshi ISHII Hiroaki NISHIKAWA Yuji INOUE 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 1997/06/25
Vol. E80-B  No. 6  pp. 907-914
Type of Manuscript:  Special Section PAPER (Special Issue on Network Operations and Management)
Category: Distribute MGNT
Keyword: 
fault managementTINAdistributed processing environmentdata-driven processorpipeline processing scheme
 Summary | Full Text:PDF(677.9KB)