Hiroaki KUNIEDA


Register-Based Process Virtual Machine Acceleration Using Hardware Extension with Hybrid Execution
Surachai THONGKAEW Tsuyoshi ISSHIKI Dongju LI Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/12/01
Vol. E98-A  No. 12  pp. 2505-2518
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
register-base VM accelerationdalvik VM accelerationHW/SW co-designed VMdynamic languages
 Summary | Full Text:PDF(4.1MB)

Retargeting Derivative-ASIP with Assembly Converter Tool
Agus BEJO Dongju LI Tsuyoshi ISSHIKI Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/05/01
Vol. E97-D  No. 5  pp. 1188-1195
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
derivative ASIPretargeting compilerLISA
 Summary | Full Text:PDF(2MB)

A Design of High Performance Parallel Architecture and Communication for Multi-ASIP Based Image Processing Engine
Hsuan-Chun LIAO Mochamad ASRI Tsuyoshi ISSHIKI Dongju LI Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/06/01
Vol. E96-A  No. 6  pp. 1222-1235
Type of Manuscript:  Special Section PAPER (Special Section on Circuit, System, and Computer Technologies)
Category: 
Keyword: 
ASIPimage processing
 Summary | Full Text:PDF(2.5MB)

A High Level Design of Reconfigurable and High-Performance ASIP Engine for Image Signal Processing
Hsuan-Chun LIAO Mochamad ASRI Tsuyoshi ISSHIKI Dongju LI Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A  No. 12  pp. 2373-2383
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
ASIPimage processing
 Summary | Full Text:PDF(2.8MB)

A Low-Cost and Energy-Efficient Multiprocessor System-on-Chip for UWB MAC Layer
Hao XIAO Tsuyoshi ISSHIKI Arif Ullah KHAN Dongju LI Hiroaki KUNIEDA Yuko NAKASE Sadahiro KIMURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/08/01
Vol. E95-D  No. 8  pp. 2027-2038
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
multiprocessor system-on-chip (MPSoC)ultra-wideband (UWB)medium access control (MAC)shared-memory
 Summary | Full Text:PDF(1.4MB)

Narrow Fingerprint Sensor Verification with Template Updating Technique
SangWoo SIN Ru ZHOU Dongju LI Tsuyoshi ISSHIKI Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/01/01
Vol. E95-A  No. 1  pp. 346-353
Type of Manuscript:  PAPER
Category: Algorithms and Data Structures
Keyword: 
fingerprintbiometricverificationtemplate updatingnarrow fingerprint sensor
 Summary | Full Text:PDF(2MB)

Practical Orientation Field Estimation for Embedded Fingerprint Recognition Systems
Yukun LIU Dongju LI Tsuyoshi ISSHIKI Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/09/01
Vol. E94-D  No. 9  pp. 1792-1799
Type of Manuscript:  PAPER
Category: Pattern Recognition
Keyword: 
fingerprint recognitionorientation fieldbinary patternembedded system
 Summary | Full Text:PDF(1MB)

Unique Fingerprint-Image-Generation Algorithm for Line Sensors
Hao NI Dongju LI Tsuyoshi ISSHIKI Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/02/01
Vol. E94-A  No. 2  pp. 781-788
Type of Manuscript:  PAPER
Category: Image
Keyword: 
biometricsfingerprintline sensorreconstructionequidistant
 Summary | Full Text:PDF(1.7MB)

Orientation Field Estimation for Embedded Fingerprint Authentication System
Wei TANG Dongju LI Tsuyoshi ISSHIKI Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/07/01
Vol. E93-D  No. 7  pp. 1918-1926
Type of Manuscript:  PAPER
Category: Pattern Recognition
Keyword: 
orientation fieldfingerprint authenticationfeature extractionbinary patternimage processing
 Summary | Full Text:PDF(663.4KB)

Entropy Decoding Processor for Modern Multimedia Applications
Sumek WISAYATAKSIN Dongju LI Tsuyoshi ISSHIKI Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12  pp. 3248-3257
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Embedded, Real-Time and Reconfigurable Systems
Keyword: 
variable length codeapplication specific processorentropy decoding engineMPEG-2MPEG-4AACH.264/AVC
 Summary | Full Text:PDF(788.1KB)

Decomposition of Task-Level Concurrency on C Programs Applied to the Design of Multiprocessor SoC
Mohammad ZALFANY URFIANTO Tsuyoshi ISSHIKI Arif ULLAH KHAN Dongju LI Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/07/01
Vol. E91-A  No. 7  pp. 1748-1756
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
task-level concurrencyhybrid dataflowC languagemultiprocessor system-on-chips
 Summary | Full Text:PDF(1006.3KB)

A Multiprocessor SoC Architecture with Efficient Communication Infrastructure and Advanced Compiler Support for Easy Application Development
Mohammad ZALFANY URFIANTO Tsuyoshi ISSHIKI Arif ULLAH KHAN Dongju LI Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/04/01
Vol. E91-A  No. 4  pp. 1185-1196
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
multiprocessor-on-a-chipsystem-on-chipscrossbar interconnectVLSI
 Summary | Full Text:PDF(1.3MB)

Low Cost SoC Design of H.264/AVC Decoder for Handheld Video Player
Sumek WISAYATAKSIN Dongju LI Tsuyoshi ISSHIKI Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/04/01
Vol. E91-A  No. 4  pp. 1197-1205
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
platform-based SoCLSI designH.264/AVC standardmobile application
 Summary | Full Text:PDF(1.1MB)

A Fingerprint Matching Using Minutia Ridge Shape for Low Cost Match-on-Card Systems
Andy SURYA RIKIN Dongju LI Tsuyoshi ISSHIKI Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/05/01
Vol. E88-A  No. 5  pp. 1305-1312
Type of Manuscript:  PAPER
Category: Digital Signal Processing
Keyword: 
biometricsfingerprintminutiae matchingminutia ridge shapesmart cardmatch-on-card
 Summary | Full Text:PDF(1.1MB)

Fast Fingerprint Classification Based on Direction Pattern
Jinqing QI Dongju LI Tsuyoshi ISSHIKI Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/08/01
Vol. E87-A  No. 8  pp. 1887-1892
Type of Manuscript:  Special Section PAPER (Special Section on Digital Signal Processing)
Category: Image/Visual Signal Processing
Keyword: 
fingerprint classificationdirection patternembedded system
 Summary | Full Text:PDF(428.2KB)

Binary Line-Pattern Algorithm for Embedded Fingerprint Authentication System
Jinqing QI Dongju LI Tsuyoshi ISSHIKI Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/08/01
Vol. E87-A  No. 8  pp. 1879-1886
Type of Manuscript:  Special Section PAPER (Special Section on Digital Signal Processing)
Category: Image/Visual Signal Processing
Keyword: 
fingerprint authenticationline-patternembedded system
 Summary | Full Text:PDF(1.9MB)

A Clock and Data Recovery PLL for Variable Bit Rate NRZ Data Using Adaptive Phase Frequency Detector
Gijun IDEI Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/06/01
Vol. E87-C  No. 6  pp. 956-963
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit and Device Technologies)
Category: 
Keyword: 
capture rangeCCOCDRclock and data recoveryfalse lockjitterNRZPFDPLLVCOz-domain analysis
 Summary | Full Text:PDF(1.8MB)

New Rate Control Method with Minimum Skipped Frames for Very Low Delay in H.263+ Codec
Trio ADIONO Tsuyoshi ISSHIKI Chawalit HONSAWEK Kazuhito ITO Dongju LI Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/06/01
Vol. E85-A  No. 6  pp. 1396-1407
Type of Manuscript:  PAPER
Category: Image
Keyword: 
H.263+rate controloptimum bit allocationlow encoder-decoder delaylip synchronization
 Summary | Full Text:PDF(1.2MB)

System-MSPA Design of H.263+ Video Encoder/Decoder LSI for Videotelephony Applications
Chawalit HONSAWEK Kazuhito ITO Tomohiko OHTSUKA Trio ADIONO Dongju LI Tsuyoshi ISSHIKI Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11  pp. 2614-2622
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Design
Keyword: 
system-MSPALSI designvideotelephony applicationsH.263+ ITU standard
 Summary | Full Text:PDF(1MB)

A New FPGA Architecture for High Performance Bit-Serial Pipeline Datapath
Akihisa OHTA Tsuyoshi ISSHIKI Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/08/25
Vol. E83-A  No. 8  pp. 1663-1672
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
FPGAbit-seriallogic block architecturerouting architecturelogic utilizationRent's rulechip scalability
 Summary | Full Text:PDF(1.6MB)

Design Optimization of VLSI Array Processor Architecture for Window Image Processing
Dongju LI Li JIANG Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/08/25
Vol. E82-A  No. 8  pp. 1475-1484
Type of Manuscript:  Special Section PAPER (Special Section on Digital Signal Processing)
Category: 
Keyword: 
image processingarray processorwindow operationsystolic array
 Summary | Full Text:PDF(1.3MB)

Dedicated Design of Motion Estimator with Bits Truncation Fast Algorithm
Li JIANG Dongju LI Shintaro HABA Chawalit HONSAWEK Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/08/25
Vol. E81-A  No. 8  pp. 1667-1675
Type of Manuscript:  Special Section PAPER (Special Section on Digital Signal Processing)
Category: 
Keyword: 
MPEGHDTVVLSIMSPAbits truncationmotion estimation
 Summary | Full Text:PDF(943.4KB)

Routability Analysis of Bit-Serial Pipeline Datapaths
Tsuyoshi ISSHIKI Wayne Wei-Ming DAI Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A  No. 10  pp. 1861-1870
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
bit-serial pipelineRent's ruleroutabilityFPGA
 Summary | Full Text:PDF(834.6KB)

FOREWORD
Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A  No. 10  pp. 1741-1741
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF(90.5KB)

A New Approach for Datapath Synthesis of Application Specific Instruction Processor
Kyung-Sik JANG Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/08/25
Vol. E80-A  No. 8  pp. 1478-1488
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
ASIPdatapath synthesisarchitecture synthesis
 Summary | Full Text:PDF(891.6KB)

Bits Truncation Adapteve Pyramid Algorithm for Motion Estimation of MPEG2
Li JIANG Kazuhito ITO Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/08/25
Vol. E80-A  No. 8  pp. 1438-1445
Type of Manuscript:  Special Section PAPER (Special Section on Digital Signal Processing)
Category: 
Keyword: 
bits truncationadaptivepyramidmotion estimationMPEG2
 Summary | Full Text:PDF(652.8KB)

Instruction Sequence Based Synthesis for Application Specific Micro-Architecture
Kyung-Sik JANG Tsuyoshi ISSHIKI Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/06/25
Vol. E80-A  No. 6  pp. 1021-1032
Type of Manuscript:  Special Section PAPER (Special Section of Papers Selected from 1996 International Technical Conference on Circuits/Systems, Computers and Communications(ITC-CSCC'96))
Category: 
Keyword: 
instruction based synthesismicro-architectureapplification specific instruction processor
 Summary | Full Text:PDF(996.6KB)

Memory Sharing Processor Array (MSPA) Architecture
Dongju LI Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/12/25
Vol. E79-A  No. 12  pp. 2086-2096
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
processor arraydata-path synthesissystolic array
 Summary | Full Text:PDF(833.2KB)

Automatic Synthesis of a Serial Input Multiprocessor Array
Dongji LI Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/12/25
Vol. E79-A  No. 12  pp. 2097-2105
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
processor arraydata-path synthesisserial interfacemultiplier
 Summary | Full Text:PDF(724.3KB)

A Cost-Effective Network for Very Large ATM Cross-Connects--The Delta Network with Expanded Middle Stages--
Takashi SHIMIZU Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 1994/11/25
Vol. E77-B  No. 11  pp. 1429-1436
Type of Manuscript:  Special Section PAPER (Special Issue on Distributed Architecture for Next Generation Communication Networks)
Category: 
Keyword: 
ATM cross-connectsmultistage interconnection networkdelta networkinternal blockingtemporarily deviating traffic
 Summary | Full Text:PDF(643.5KB)

Distributed Load Balancing Schemes for Parallel Video Encoding System
Zhaochen HUANG Yoshinori TAKEUCHI Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/05/25
Vol. E77-A  No. 5  pp. 923-930
Type of Manuscript:  PAPER
Category: Parallel/Multidimensional Signal Processing
Keyword: 
distributed load balancingconvergencevideo encodingparallel processing
 Summary | Full Text:PDF(700.8KB)

The lmprovement in Performance-Driven Analog LSI Layout System LIBRA
Tomohiko OHTSUKA Nobuyuki KUROSAWA Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/10/25
Vol. E76-A  No. 10  pp. 1626-1635
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
process parameterwire parasiticsdevice heatperformance specificationpenalty functionsimulated annealingrip-up rerouting
 Summary | Full Text:PDF(820.2KB)

RHINE: Reconfigurable Multiprocessor System for Video CODEC
Yoshinori TAKEUCHI Zhao-Chen HUANG Masatomo SAEKI Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/06/25
Vol. E76-A  No. 6  pp. 947-956
Type of Manuscript:  Special Section PAPER (Special Section on Papers Selected from 1992 Joint Technical Conference on Circuits/Systems,Computers and Communications (JTC-CSCC'92))
Category: Methods and Circuits for Signal Processing
Keyword: 
parallel processingload balancingvideo CODECparallel architecturereconfigurable architecture
 Summary | Full Text:PDF(823.2KB)

Space Partitioning Image Processing Technique for Parallel Recursive Half Toning
Yoshinori TAKEUCHI Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/04/25
Vol. E76-A  No. 4  pp. 603-612
Type of Manuscript:  PAPER
Category: Digital Signal Processing
Keyword: 
parallel processingrecursive filteringdigital half toneparallel algorithmspace partitioning processing
 Summary | Full Text:PDF(887.8KB)

Modularization and Processor Placement for DSP Neo-Systolic Array
Kazuhito ITO Kesami HAGIWARA Takashi SHIMIZU Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/03/25
Vol. E76-A  No. 3  pp. 349-361
Type of Manuscript:  Special Section PAPER (Special Section on the 5th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
VLSI system compilerVLSI signal processingneo-systolic array
 Summary | Full Text:PDF(1.1MB)

Parallel Processing Architecture Design for Two-Dimensional Image Processing Using Spatial Expansion of the Signal Flow Graph
Tsuyoshi ISSHIKI Yoshinori TAKEUCHI Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/03/25
Vol. E76-A  No. 3  pp. 337-348
Type of Manuscript:  Special Section PAPER (Special Section on the 5th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
architecture designspatial expansion of SFGpixel SFGframe SFG
 Summary | Full Text:PDF(1.1MB)

VIRGO: Hierarchical DSP Code Generator Based on Vectorized Signal Flow Graph Description
Norichika KUMAMOTO Keiji AOKI Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/08/25
Vol. E75-A  No. 8  pp. 1004-1013
Type of Manuscript:  Special Section PAPER (Special Section on the 6th Digital Signal Processing Symposium)
Category: 
Keyword: 
digital signal processorcode generationhierarchical schedulingvectorized-signal flow graph
 Summary | Full Text:PDF(787.1KB)

LIBRA: Automatic Performance-Driven Layout for Analog LSIs
Tomohiko OHTSUKA Hiroaki KUNIEDA Mineo KANEKO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1992/03/25
Vol. E75-C  No. 3  pp. 312-321
Type of Manuscript:  Special Section PAPER (Special Issue on Analog LSI and Related Technology)
Category: 
Keyword: 
performance-drivenprocess parameterwire parasiticsperformance deviationsimulated annealingLIBRA
 Summary | Full Text:PDF(854.8KB)

Two-Dimensional Quadrilateral Recursive Digital Filters with Parallel Structure--Synthesis and Parallel Processing--
Tsuyoshi ISSHIKI Hiroaki KUNIEDA Mineo KANEKO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/03/25
Vol. E75-A  No. 3  pp. 352-361
Type of Manuscript:  Special Section PAPER (Special Section on the 4th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
quadrilateral recursive filtersparallel processing
 Summary | Full Text:PDF(672.8KB)

An Optimum Placement of Capacitors in the Layout of Switched Capacitor Networks
Mineo KANEKO Kimihiko KAZUI Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/02/25
Vol. E75-A  No. 2  pp. 215-223
Type of Manuscript:  PAPER
Category: Analog Circuits and Signal Processing
Keyword: 
analog signal processingVLSI design technology
 Summary | Full Text:PDF(521.2KB)

Two Dimensional Space Partition Recursive Filtering Algorithm on Rectangular Processor Array
Yoshinori TAKEUCHI Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1991/01/25
Vol. E74-A  No. 1  pp. 42-48
Type of Manuscript:  PAPER
Category: Digital Signal Processing
Keyword: 
 Summary | Full Text:PDF(652.1KB)