Hidetsugu IRIE

Using Cacheline Reuse Characteristics for Prefetcher Throttling
Hidetsugu IRIE  Takefumi MIYOSHI  Goki HONJO  Kei HIRAKI  Tsutomu YOSHINAGA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/12/01
Vol. E95-D  No. 12  pp. 2928-2938
Type of Manuscript: Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: Computer Architecture
Keyword: 
microarchitecture,  cache,  prefetch, 
  Summary |  Full Text:PDF (1.6MB)
Computation-Communication Overlap of Linpack on a GPU-Accelerated PC Cluster
Junichi OHMURA  Takefumi MIYOSHI  Hidetsugu IRIE  Tsutomu YOSHINAGA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/12/01
Vol. E94-D  No. 12  pp. 2319-2327
Type of Manuscript: Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: 
Keyword: 
parallel processing,  multi-core processor,  GPU,  computation-communication overlap, 
  Summary |  Full Text:PDF (637.1KB)
Ultra Dependable Processor
Shuichi SAKAI  Masahiro GOSHIMA  Hidetsugu IRIE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/09/01
Vol. E91-C  No. 9  pp. 1386-1393
Type of Manuscript: Special Section PAPER (Special Section on Advanced Processors Based on Novel Concepts in Computation)
Category: INVITED
Keyword: 
microprocessor architecture,  dependable computing,  attacks,  faults,  errors,  failures,  soft errors,  timing errors,  tamper resistance,  information flow,  injection attack,  dependability manager, 
  Summary |  Full Text:PDF (1.1MB)