Hidetoshi ONODERA


A Necessary and Sufficient Condition of Supply and Threshold Voltages in CMOS Circuits for Minimum Energy Point Operation
Jun SHIOMI Tohru ISHIHARA Hidetoshi ONODERA 
Publication:   
Publication Date: 2017/12/01
Vol. E100-A  No. 12  pp. 2764-2775
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
minimum energy point tracking (MEPT)dynamic voltage and frequency scaling (DVFS)adaptive body biasing (ABB)standard-cell based memory (SCM)
 Summary | Full Text:PDF(2MB)

A Minimum Energy Point Tracking Algorithm Based on Dynamic Voltage Scaling and Adaptive Body Biasing
Shu HOKIMOTO Tohru ISHIHARA Hidetoshi ONODERA 
Publication:   
Publication Date: 2017/12/01
Vol. E100-A  No. 12  pp. 2776-2784
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
minimum energy point tracking (MEPT)dynamic voltage and frequency scaling (DVFS)adaptive body biasing (ABB)
 Summary | Full Text:PDF(1.4MB)

Analytical Stability Modeling for CMOS Latches in Low Voltage Operation
Tatsuya KAMAKARI Jun SHIOMI Tohru ISHIHARA Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/12/01
Vol. E99-A  No. 12  pp. 2463-2472
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
latchlow voltage designstability modeling
 Summary | Full Text:PDF(2.9MB)

Statistical Timing Modeling Based on a Lognormal Distribution Model for Near-Threshold Circuit Optimization
Jun SHIOMI Tohru ISHIHARA Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/07/01
Vol. E98-A  No. 7  pp. 1455-1466
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
near-threshold computingstatistical static timing analysis (SSTA)
 Summary | Full Text:PDF(1.7MB)

A Forward/Reverse Body Bias Generator with Wide Supply-Range down to Threshold Voltage
Norihiro KAMAE Akira TSUCHIYA Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2015/06/01
Vol. E98-C  No. 6  pp. 504-511
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
body bias generatordynamic voltage frequency scalinglow supply voltageanalog-assisted digitalswitched-capacitor circuits
 Summary | Full Text:PDF(1MB)

Impact of Cell Distance and Well-contact Density on Neutron-induced Multiple Cell Upsets
Jun FURUTA Kazutoshi KOBAYASHI Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2015/04/01
Vol. E98-C  No. 4  pp. 298-303
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design---Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
Neutron-induced Soft ErrorMultiple Cell Upset (MCU)cell distancewell-contact densityFlip-Flop
 Summary | Full Text:PDF(796.1KB)

Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing
Hiroaki KONOURA Dawood ALNAJJAR Yukio MITSUYAMA Hajime SHIMADA Kazutoshi KOBAYASHI Hiroyuki KANBARA Hiroyuki OCHI Takashi IMAGAWA Kazutoshi WAKABAYASHI Masanori HASHIMOTO Takao ONOYE Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/12/01
Vol. E97-A  No. 12  pp. 2518-2529
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
reconfigurable architecturesoft errorradiation testbehavioral synthesisstate machine
 Summary | Full Text:PDF(3.8MB)

Radiation-Hardened PLL with a Switchable Dual Modular Redundancy Structure
SinNyoung KIM Akira TSUCHIYA Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2014/04/01
Vol. E97-C  No. 4  pp. 325-331
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design,---,Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
radiation-hardened phase-locked loop (RH-PLL)PLLradiation-hardened-by-design (RHBD)dual modular redundancy (DMR)
 Summary | Full Text:PDF(3.8MB)

A Body Bias Generator with Low Supply Voltage for Within-Die Variability Compensation
Norihiro KAMAE Akira TSUCHIYA Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/03/01
Vol. E97-A  No. 3  pp. 734-740
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
body bias generatordynamic voltage frequency scalinganalog-assisted digitallow supply voltage
 Summary | Full Text:PDF(1.5MB)

Analysis of Radiation-Induced Clock-Perturbation in Phase-Locked Loop
SinNyoung KIM Akira TSUCHIYA Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/03/01
Vol. E97-A  No. 3  pp. 768-776
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
radiation-hardened phase-locked loop (RH-PLL)soft errorclock-perturbation model
 Summary | Full Text:PDF(2.6MB)

Standard Cell Structure with Flexible P/N Well Boundaries for Near-Threshold Voltage Operation
Shinichi NISHIZAWA Tohru ISHIHARA Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/12/01
Vol. E96-A  No. 12  pp. 2499-2507
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword: 
standard cell designlow power circuit designnear threshold operationPN ratio optimization
 Summary | Full Text:PDF(2MB)

On-Chip Detection of Process Shift and Process Spread for Post-Silicon Diagnosis and Model-Hardware Correlation
A.K.M. Mahfuzul ISLAM Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/09/01
Vol. E96-D  No. 9  pp. 1971-1979
Type of Manuscript:  Special Section PAPER (Special Section on Dependable Computing)
Category: 
Keyword: 
process shiftprocess spreadmonitor structurepost-silicon analysisdelay testadaptive test
 Summary | Full Text:PDF(898KB)

A Radiation-Hard Redundant Flip-Flop to Suppress Multiple Cell Upset by Utilizing the Parasitic Bipolar Effect
Kuiyuan ZHANG Jun FURUTA Ryosuke YAMAMOTO Kazutoshi KOBAYASHI Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/04/01
Vol. E96-C  No. 4  pp. 511-517
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
DMRsoft errorMCUdevice simulation
 Summary | Full Text:PDF(2MB)

Area-Effective Inductive Peaking with Interwoven Inductor for High-Speed Laser-Diode Driver for Optical Communication System
Takeshi KUBOKI Yusuke OHTOMO Akira TSUCHIYA Keiji KISHINE Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/02/01
Vol. E95-A  No. 2  pp. 479-486
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
interwoven inductorLD driveroptical communication
 Summary | Full Text:PDF(4.4MB)

Variation-Tolerance of a 65-nm Error-Hardened Dual-Modular-Redundancy Flip-Flop Measured by Shift-Register-Based Monitor Structures
Chikara HAMANAKA Ryosuke YAMAMOTO Jun FURUTA Kanto KUBOTA Kazutoshi KOBAYASHI Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12  pp. 2669-2675
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
soft errorhardened designvariabilitytest structureshift register
 Summary | Full Text:PDF(3.1MB)

An Area/Delay Efficient Dual-Modular Flip-Flop with Higher SEU/SET Immunity
Jun FURUTA Kazutoshi KOBAYASHI Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/03/01
Vol. E93-C  No. 3  pp. 340-346
Type of Manuscript:  Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category: 
Keyword: 
TMRbuilt-in soft errorSEUSET
 Summary | Full Text:PDF(385.2KB)

Statistical Gate Delay Model for Multiple Input Switching
Takayuki FUKUOKA Akira TSUCHIYA Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12  pp. 3070-3078
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Device and Circuit Modeling and Analysis
Keyword: 
statistical static timing analysismultiple input switchingstatistical maximum operation
 Summary | Full Text:PDF(442.6KB)

Analytical Model of Static Noise Margin in CMOS SRAM for Variation Consideration
Hirofumi SHINOHARA Koji NII Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/09/01
Vol. E91-C  No. 9  pp. 1488-1500
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
SRAMmemory cellstatic noise marginSNMvariability
 Summary | Full Text:PDF(803.7KB)

Timing Analysis Considering Temporal Supply Voltage Fluctuation
Masanori HASHIMOTO Junji YAMAGUCHI Takashi SATO Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/03/01
Vol. E91-D  No. 3  pp. 655-660
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSIs)
Category: Verification and Timing Analysis
Keyword: 
timing analysisdynamic power supply noise
 Summary | Full Text:PDF(450.7KB)

Manufacturability-Aware Design of Standard Cells
Hirokazu MUTA Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/12/01
Vol. E90-A  No. 12  pp. 2682-2690
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Design
Keyword: 
manufacturabilityvariabilityDFMACLVstandard cellOPCRET
 Summary | Full Text:PDF(546.5KB)

Timing Analysis Considering Spatial Power/Ground Level Variation
Masanori HASHIMOTO Junji YAMAGUCHI Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/12/01
Vol. E90-A  No. 12  pp. 2661-2668
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Design
Keyword: 
timing analysispower supply noisegate delay modelpower/ground level variation
 Summary | Full Text:PDF(497.6KB)

A 90 nm 4848 LUT-Based FPGA Enhancing Speed and Yield Utilizing Within-Die Delay Variations
Kazutoshi KOBAYASHI Kazuya KATSUKI Manabu KOTANI Yuuri SUGIHARA Yohei KUME Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/10/01
Vol. E90-C  No. 10  pp. 1919-1926
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Technology toward Frontiers of New Market)
Category: Low-Power and High-Performance VLSI Circuit Technology
Keyword: 
variation-awarereconfigurable deviceFPGAyieldDFM
 Summary | Full Text:PDF(689.6KB)

Low-Power Design of CML Driver for On-Chip Transmission-Lines Using Impedance-Unmatched Driver
Takeshi KUBOKI Akira TSUCHIYA Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/06/01
Vol. E90-C  No. 6  pp. 1274-1281
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
on-chip signalingcurrent-mode logic
 Summary | Full Text:PDF(690.2KB)

Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling
Akira TSUCHIYA Masanori HASHIMOTO Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/06/01
Vol. E90-C  No. 6  pp. 1267-1273
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
on-chip transmission-linetermination
 Summary | Full Text:PDF(855.9KB)

A 90 nm LUT Array for Speed and Yield Enhancement by Utilizing Within-Die Delay Variations
Kazuya KATSUKI Manabu KOTANI Kazutoshi KOBAYASHI Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/04/01
Vol. E90-C  No. 4  pp. 699-707
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
Category: Digital
Keyword: 
within-die variationreconfigurable deviceFPGALUT (look-up table)yield
 Summary | Full Text:PDF(663.5KB)

Interconnect RL Extraction Based on Transfer Characteristics of Transmission-Line
Akira TSUCHIYA Masanori HASHIMOTO Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12  pp. 3585-3593
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Interconnect
Keyword: 
parameter extractiontransmission-linefrequency dependence
 Summary | Full Text:PDF(450.9KB)

FOREWORD
Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12  pp. 3377-3377
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF(58.6KB)

Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design
Toshiki KANAMOTO Tatsuhiko IKEDA Akira TSUCHIYA Hidetoshi ONODERA Masanori HASHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12  pp. 3560-3568
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Interconnect
Keyword: 
substrateinterconnectresistanceinductanceSoC
 Summary | Full Text:PDF(1.4MB)

A Leakage Reduction Scheme for Sleep Transistors with Decoupling Capacitors in the Deep Submicron Era
Kazutoshi KOBAYASHI Akihiko HIGUCHI Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/06/01
Vol. E89-C  No. 6  pp. 838-843
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
sleep transistordecoupling capacitorMTCMOSlow power
 Summary | Full Text:PDF(442KB)

Variability: Modeling and Its Impact on Design
Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/03/01
Vol. E89-C  No. 3  pp. 342-348
Type of Manuscript:  INVITED PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era)
Category: 
Keyword: 
variabilitywithin-die variabilitydie-to-die variabilitystatistical design
 Summary | Full Text:PDF(528.9KB)

Alternate Self-Shielding for High-Speed and Reliable On-Chip Global Interconnect
Yoichi YUYAMA Akira TSUCHIYA Kazutoshi KOBAYASHI Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/03/01
Vol. E89-C  No. 3  pp. 327-333
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era)
Category: Interface and Interconnect Techniques
Keyword: 
alternate self shieldingon-chip global interconnectcritical transition and bus encoding
 Summary | Full Text:PDF(876.3KB)

Statistical Analysis of Clock Skew Variation in H-Tree Structure
Masanori HASHIMOTO Tomonori YAMAMOTO Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12  pp. 3375-3381
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Prediction and Analysis
Keyword: 
clock skewmanufacturing variabilityenvironmental variabilitytransition time constraintstatistical analysisclock distribution
 Summary | Full Text:PDF(826.7KB)

Successive Pad Assignment for Minimizing Supply Voltage Drop
Takashi SATO Masanori HASHIMOTO Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12  pp. 3429-3436
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Power/Ground Network
Keyword: 
successive pad assignment (SPA)incremental matrix inversion (IMI)voltage droppower distribution network
 Summary | Full Text:PDF(557.9KB)

Effects of On-Chip Inductance on Power Distribution Grid
Atsushi MURAMATSU Masanori HASHIMOTO Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12  pp. 3564-3572
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
power distribution networkon-chip inductancepower supply noisedecoupling capacitance
 Summary | Full Text:PDF(789.2KB)

A Resource-Shared VLIW Processor for Low-Power On-Chip Multiprocessing in the Nanometer Era
Kazutoshi KOBAYASHI Masao ARAMOTO Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/04/01
Vol. E88-C  No. 4  pp. 552-558
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP)
Category: Digital
Keyword: 
parallel processingVLIWSMTlow powernanometerleakage power
 Summary | Full Text:PDF(1.1MB)

Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling
Akira TSUCHIYA Masanori HASHIMOTO Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/04/01
Vol. E88-A  No. 4  pp. 885-891
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
global interconnecthigh-speed signalingperformance limitation
 Summary | Full Text:PDF(1MB)

A Performance Prediction of Clock Generation PLLs: A Ring Oscillator Based PLL and an LC Oscillator Based PLL
Takahito MIYAZAKI Masanori HASHIMOTO Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/03/01
Vol. E88-C  No. 3  pp. 437-444
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
clock generation PLLLC oscillatorring oscillatorperformance predictionjitterpower consumptionchip area
 Summary | Full Text:PDF(401.8KB)

Crosstalk Noise Optimization by Post-Layout Transistor Sizing
Masanori HASHIMOTO Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12  pp. 3251-3257
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Design
Keyword: 
crosstalk noisecapacitive coupling noisetransistor sizinggate sizingpost-layout optimization
 Summary | Full Text:PDF(300.4KB)

Design Optimization Methodology for On-Chip Spiral Inductors
Kenichi OKADA Hiroaki HOSHINO Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/06/01
Vol. E87-C  No. 6  pp. 933-941
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit and Device Technologies)
Category: 
Keyword: 
spiral inductorresponse surface methodoptimizationquality factor
 Summary | Full Text:PDF(1000.8KB)

Instruction-Level Power Estimation Method by Considering Hamming Distance of Registers
Akihiko HIGUCHI Kazutoshi KOBAYASHI Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/04/01
Vol. E87-A  No. 4  pp. 823-829
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 16th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
embedded processorpower estimationinstruction-level
 Summary | Full Text:PDF(1.3MB)

A Comprehensive Simulation and Test Environment for Prototype VLSI Verification
Kazutoshi KOBAYASHI Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/03/01
Vol. E87-D  No. 3  pp. 630-636
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSI)
Category: Verification
Keyword: 
simulationtestVLSItesterverification
 Summary | Full Text:PDF(1.4MB)

An Efficient Motion Estimation Algorithm Using a Gyro Sensor
Kazutoshi KOBAYASHI Ryuta NAKANISHI Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/03/01
Vol. E87-A  No. 3  pp. 530-538
Type of Manuscript:  Special Section PAPER (Special Section on Applications and Implementations of Digital Signal Processing)
Category: Video/Image Coding
Keyword: 
motion estimationgyro sensorMPEG-4
 Summary | Full Text:PDF(537.9KB)

Experimental Study on Cell-Base High-Performance Datapath Design
Masanori HASHIMOTO Yoshiteru HAYASHI Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12  pp. 3204-3207
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: IP Design
Keyword: 
datapath designbit-slice layouttransistor sizingcell-base design
 Summary | Full Text:PDF(227.8KB)

Crosstalk Noise Estimation for Generic RC Trees
Masanori HASHIMOTO Masao TAKAHASHI Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12  pp. 2965-2973
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Parasitics and Noise
Keyword: 
crosstalk noisecapacitive couplingnoise estimationsignal integrity
 Summary | Full Text:PDF(854.2KB)

Representative Frequency for Interconnect R(f)L(f)C Extraction
Akira TSUCHIYA Masanori HASHIMOTO Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12  pp. 2942-2951
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Parasitics and Noise
Keyword: 
interconnectextractionfrequency-dependent
 Summary | Full Text:PDF(788KB)

Statistical Gate-Delay Modeling with Intra-Gate Variability
Kenichi OKADA Kento YAMAOKA Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12  pp. 2914-2922
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Parasitics and Noise
Keyword: 
intra-chip variabilitystatistical timing analysisintra-gate variabilitymanufacturing fluctuation
 Summary | Full Text:PDF(677.1KB)

Realistic Delay Calculation Based on Measured Intra-Chip and Inter-Chip Variabilities with the Size Dependence
Kenichi OKADA Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/04/01
Vol. E86-A  No. 4  pp. 746-751
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 15th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
intra-chip variabilitystatistical timing analysismanufacturing fluctuation
 Summary | Full Text:PDF(384.7KB)

Increase in Delay Uncertainty by Performance Optimization
Masanori HASHIMOTO Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A  No. 12  pp. 2799-2802
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: Timing Analysis
Keyword: 
performance optimizationdelay increasestatistical timing analysisdelay uncertaintytransistor sizing
 Summary | Full Text:PDF(297.5KB)

A Dynamically Phase Adjusting PLL for Improvement of Lock-up Performance
Takeo YASUDA Hiroaki FUJITA Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11  pp. 2793-2801
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Analog Design
Keyword: 
PLLphase adjustvariable delaylock-up
 Summary | Full Text:PDF(1.4MB)

FOREWORD
Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11  pp. 2613-2613
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF(26.2KB)

Post-Layout Transistor Sizing for Power Reduction in Cell-Base Design
Masanori HASHIMOTO Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11  pp. 2769-2777
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Optimization of Power and Timing
Keyword: 
transistor sizinglow power designcell-base designpost-layout optimizationgate sizing
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A Hierarchical Statistical Optimization Method Driven by Constraint Generation Based on Mahalanobis' Distance
Tomohiro FUJITA Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/03/01
Vol. E84-A  No. 3  pp. 727-734
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 13th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
analog LSIyield optimizationhierarchical designconstraint generationMahalanobis' distance
 Summary | Full Text:PDF(485.5KB)

A Low-Power High-Performance Vector-Pipeline DSP for Low-Rate Videophones
Kazutoshi KOBAYASHI Makoto EGUCHI Takuya IWAHASHI Takehide SHIBAYAMA Xiang LI Kosuke TAKAI Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/02/01
Vol. E84-C  No. 2  pp. 193-201
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Power High-Performance VLSI Processors and Technologies)
Category: 
Keyword: 
VLSIDSPMSHVQvideophonevideo compression
 Summary | Full Text:PDF(1001.1KB)

Statistical Modeling of Device Characteristics with Systematic Variability
Kenichi OKADA Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/02/01
Vol. E84-A  No. 2  pp. 529-536
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques Supporting the System LSI Era)
Category: 
Keyword: 
MOSFETvariabilitysystematicstochastic
 Summary | Full Text:PDF(325.2KB)

A Method for Linking Process-Level Variability to System Performances
Tomohiro FUJITA Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12  pp. 2592-2599
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Simulation
Keyword: 
analog VLSI circuitstatistical analysishierarchical analysisresponse surface modelintermediate mode
 Summary | Full Text:PDF(522.8KB)

A Performance Optimization Method by Gate Resizing Based on Statistical Static Timing Analysis
Masanori HASHIMOTO Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12  pp. 2558-2568
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Performance Optimization
Keyword: 
statistical static timing analysisstatic timing analysisgate resizingtransistor sizingperformance optimization
 Summary | Full Text:PDF(418.4KB)

Architecture and Performance Evaluation of a New Functional Memory: Functional Memory for Addition
Kazutoshi KOBAYASHI Masanao YAMAOKA Yukifumi KOBAYASHI Hidetoshi ONODERA Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12  pp. 2400-2408
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Architecture
Keyword: 
VLSIfunctional memoryDRAMparallel processorblock matching
 Summary | Full Text:PDF(868.6KB)

A Real-Time Low-Rate Video Compression Algorithm Using Multi-Stage Hierarchical Vector Quantization
Kazutoshi KOBAYASHI Kazuhiko TERADA Hidetoshi ONODERA Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/02/25
Vol. E82-A  No. 2  pp. 215-222
Type of Manuscript:  Special Section PAPER (Special Section on VLSI for Digital Signal Processing)
Category: 
Keyword: 
vector quantizationfunctional memoryparallel processorlow-rate image compressionnoise robustnessMSHVQ
 Summary | Full Text:PDF(665.6KB)

Layout Dependent Matching Analysis of CMOS Circuits
Kenichi OKADA Hidetoshi ONODERA Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/02/25
Vol. E82-A  No. 2  pp. 348-355
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
CMOSmatchingmicro-loading-effectfluctuation
 Summary | Full Text:PDF(168.8KB)

A Power and Delay Optimization Method Using Input Reordering in Cell-Based CMOS Circuits
Masanori HASHIMOTO Hidetoshi ONODERA Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/01/25
Vol. E82-A  No. 1  pp. 159-166
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
input reorderingtransistor reorderingpower estimation
 Summary | Full Text:PDF(317.8KB)

An LSI for Low Bit-Rate Image Compression Using Vector Quantization
Kazutoshi KOBAYASHI Noritsugu NAKAMURA Kazuhiko TERADA Hidetoshi ONODERA Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/05/25
Vol. E81-C  No. 5  pp. 718-724
Type of Manuscript:  Special Section PAPER (Special Issue on Multimedia, Network, and DRAM LSIs)
Category: 
Keyword: 
parallel processormemory-basedvector quantizationlow bit-rate image compressionlow powerSIMD
 Summary | Full Text:PDF(748.2KB)

Analytical Formulas of Output Waveform and Short-Circuit Power Dissipation for Static CMOS Gates Driving a CRC π Load
Akio HIRATA Hidetoshi ONODERA Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/03/25
Vol. E81-A  No. 3  pp. 462-469
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 10th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
short-circuit power dissipationshort-circuit currentresistive-capacitive loadCRC π loadoutput waveformgate delay
 Summary | Full Text:PDF(567.7KB)

A Memory-Based Parallel Processor for Vector Quantization: FMPP-VQ
Kazutoshi KOBAYASHI Masayoshi KINOSHITA Hidetoshi ONODERA Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/07/25
Vol. E80-C  No. 7  pp. 970-975
Type of Manuscript:  Special Section PAPER (Special Issue on New Concept Device and Novel Architecture LSIs)
Category: Multi Processors
Keyword: 
parallel processormemory-basevector quantizationlow bit-rate image compressionSIMD
 Summary | Full Text:PDF(632KB)

A Current Mode Cyclic A/D Converter with Submicron Processes
Masaki KONDO Hidetoshi ONODERA Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/02/25
Vol. E80-A  No. 2  pp. 360-364
Type of Manuscript:  Special Section LETTER (Special Section on Analog Circuit Techniques for System-on-Chip Integration)
Category: 
Keyword: 
A/DA/D convertercurrent moderatio-independentRGC
 Summary | Full Text:PDF(341.3KB)

Estimation of short-Circuit Power Dissipation for Static CMOS Gates
Akio HIRATA Hidetoshi ONODERA Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/03/25
Vol. E79-A  No. 3  pp. 304-311
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
short-circuit power dissipationshort-circit currentsimulation of power dissipationlow power disignpower estimation
 Summary | Full Text:PDF(566.4KB)

Model-Adaptable Parameter Extraction System for MOSFET Models
Masaki KONDO Takashi MORIE Hidetoshi ONODERA Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/05/25
Vol. E78-A  No. 5  pp. 569-572
Type of Manuscript:  Special Section LETTER (Special Section of Letters Selected from the 1994 IEICE Fall Conference)
Category: 
Keyword: 
parameter extraction systeminitial value estimationMOSFET characterization
 Summary | Full Text:PDF(272.1KB)

Development of Module Generators from Extracted Design Procedures--Application to Analog Device Generation--
Takashi MORIE  Hidetoshi ONODERA Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/02/25
Vol. E78-A  No. 2  pp. 160-168
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Computer Aided Design)
Category: 
Keyword: 
device layoutmodule generationanalog LSIstore and re-usedesign procedure
 Summary | Full Text:PDF(888.4KB)

Compaction with Shape Optimization and Its Application to Layout Recycling
Kazuhisa OKADA Hidetoshi ONODERA Keikichi TAMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/02/25
Vol. E78-A  No. 2  pp. 169-176
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Computer Aided Design)
Category: 
Keyword: 
analog layoutcompactionshape optimizationlayout recycling
 Summary | Full Text:PDF(730.8KB)

Experiments with Power Optimization in Gate Sizing
Guangqiu CHEN Hidetoshi ONODERA Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/11/25
Vol. E77-A  No. 11  pp. 1913-1916
Type of Manuscript:  Special Section LETTER (Special Section of Letters Selected from the 1994 IEICE Spring Conference)
Category: 
Keyword: 
low power designpower dissipationgate sizingarea–power–delay tradeoff
 Summary | Full Text:PDF(267.1KB)

A Bit-Parallel Block-Parallel Functional Memory Type Parallel Processor Architecture
Kazutoshi KOBAYASHI Keikichi TAMARU Hiroto YASUURA Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/07/25
Vol. E76-C  No. 7  pp. 1151-1158
Type of Manuscript:  Special Section PAPER (Special Issue on New Architecture LSIs)
Category: Memory-Based Parallel Processor Architectures
Keyword: 
parallel processormemory-based simple structurelogical and arithmetic operations
 Summary | Full Text:PDF(734.9KB)

Hardware Architecture for Kohonen Network
Hidetoshi ONODERA Kiyoshi TAKESHITA Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/07/25
Vol. E76-C  No. 7  pp. 1159-1166
Type of Manuscript:  Special Section PAPER (Special Issue on New Architecture LSIs)
Category: Neural Networks and Chips
Keyword: 
neural networkKohonen networkmassively parallel computationcontent addressable memory
 Summary | Full Text:PDF(712.9KB)

Module Generation of a CMOS Op Amp Using a Non-linear Optimization Method
Hidetoshi ONODERA Hiroyuki KANBARA Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1988/10/25
Vol. E71-E  No. 10  pp. 947-949
Type of Manuscript:  Special Section LETTER (Special Issue: Papers from 1988 Autumn Convention IEICE)
Category: Integrated Circuit
Keyword: 
 Summary | Full Text:PDF(203.6KB)