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Hideto HIDAKA

A Board Level Parallel Test Circuit and a Short Circuit Failure Repair Circuit for High-Density, Low-Power DRAMs Kiyohiro FURUTANI Tsukasa OOISHI Mikio ASAKURA Hideto HIDAKA Hideyuki OZAKI Michihiro YAMADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/04/20 Vol. E80-C No. 4 pp. 582-589 Type of Manuscript: Special Section PAPER (Special Issue on Circuit Technologies for Memory and Analog LSIs) Category: Keyword: DRAM, test, redundancy,
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A Mixed-Mode Voltage Down Converter with Impedance Adjustment Circuitry for Low-Voltage High-Frequency Memories Tsukasa OOISHI Yuichiro KOMIYA Kei HAMADE Mikio ASAKURA Kenichi YASUDA Kiyohiro FURUTANI Tetsuo KATO Hideto HIDAKA Hideyuki OZAKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/07/20 Vol. E79-C No. 7 pp. 986-996 Type of Manuscript: Special Section PAPER (Special Issue on the 1995 Symposium on VLSI Circuits (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.31, No.4 April 1996)) Category: Memory Keyword:
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Features of SOI DRAM's and their Potential for Low-Voltage and/or Giga-Bit Scale DRAM's Yasuo YAMAGUCHI Toshiyuki OASHI Takahisa EIMORI Toshiaki IWAMATSU Shouichi MITAMOTO Katsuhiro SUMA Takahiro TSURUDA Fukashi MORISHITA Masakazu HIROSE Hideto HIDAKA Kazutami ARIMOTO Kazuyasu FUJISHIMA Yasuo INOUE Tadashi NISHIMURA Hirokazu MIYOSHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/06/20 Vol. E79-C No. 6 pp. 772-780 Type of Manuscript: INVITED PAPER (Special Issue on ULSI Memory Technology) Category: Dynamic RAMs Keyword: SOL, SIMOX, DRAM, low-voltage operation,
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An Automatic Temperature Compensation of Internal Sense Ground for Subquarter Micron DRAM's Tsukasa OOISHI Yuichiro KOMIYA Kei HAMADE Mikio ASAKURA Kenichi YASUDA Kiyohiro FURUTANI Hideto HIDAKA Hiroshi MIYAMOTO Hideyuki OZAKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/06/20 Vol. E78-C No. 6 pp. 719-727 Type of Manuscript: Special Section PAPER (Special Issue on the 1994 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol. 30, No. 4 April 1995)) Category: Keyword:
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A Well-Synchronized Sensing/Equalizing Method for Sub-1.0-V Operating Advanced DRAM's Tsukasa OOISHI Mikio ASAKURA Shigeki TOMISHIMA Hideto HIDAKA Kazutami ARIMOTO Kazuyasu FUJISHIMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1994/05/20 Vol. E77-C No. 5 pp. 762-770 Type of Manuscript: Special Section PAPER (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994)) Category: Keyword:
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A Smart Design Methodology with Distributed Extra Gate-Arrays for Advanced ULSI Memories Masaki TSUKUDA Kazutami ARIMOTO Mikio ASAKURA Hideto HIDAKA Kazuyasu FUJISHIMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/11/20 Vol. E76-C No. 11 pp. 1589-1594 Type of Manuscript: Special Section PAPER (Special Issue on LSI Memories) Category: DRAM Keyword: reduction of design TAT, design methodology, ULSI memory,
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A ST (Stretchable Memory Matrix) DRAM with Multi-Valued Addressing Scheme Tsukasa OOISHI Mikio ASAKURA Hideto HIDAKA Kazutami ARIMOTO Kazuyasu FUJISHIMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1992/11/20 Vol. E75-C No. 11 pp. 1323-1332 Type of Manuscript: Special Section PAPER (Special Issue on LSI Memories) Category: Keyword: multi-valued addressing scheme,
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A New Array Architecture for 16 Mb DRAMs with Special Page Mode Masaki TSUKUDE Tsukasa OISHI Kazutami ARIMOTO Hideto HIDAKA Kazuyasu FUJISHIMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1992/10/20 Vol. E75-C No. 10 pp. 1267-1274 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: array architecture, dynamic memory, high speed access, wide operating margin, low power dissipation,
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A High-Density Dual-Port Memory Cell Operation and Array Architecture for ULSI DRAM's Hideto HIDAKA Kazutami ARIMOTO Kazuyasu FUJISHIMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1992/04/20 Vol. E75-C No. 4 pp. 508-515 Type of Manuscript: Special Section PAPER (Joint Special Issue on the 1991 VLSI Circuits Symposium) Category: Keyword:
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A Dual-Mode Sensing Scheme of Capacitor-Coupled EEPROM Cell Masanori HAYASHIKOSHI Hideto HIDAKA Kazutami ARIMOTO Kazuyasu FUJISHIMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1992/04/20 Vol. E75-C No. 4 pp. 467-471 Type of Manuscript: Special Section PAPER (Joint Special Issue on the 1991 VLSI Circuits Symposium) Category: Keyword:
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Cell-Plate Line Connecting Complementary Bit-Line (C³) Architecture for Battery-Operating DRAM's Mikio ASAKURA Kazutami ARIMOTO Hideto HIDAKA Kazuyasu FUJISHIMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1992/04/20 Vol. E75-C No. 4 pp. 495-500 Type of Manuscript: Special Section PAPER (Joint Special Issue on the 1991 VLSI Circuits Symposium) Category: Keyword:
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A Divided/Pausing Bitline Sensing Scheme (DIPS) for ULSI DRAM Core Hideto HIDAKA Yoshio MATSUDA Kazuyasu FUJISHIMA
Publication: IEICE TRANSACTIONS (1976-1990) Publication Date: 1990/11/20 Vol. E73-E No. 11 pp. 1852-1854 Type of Manuscript: Special Section LETTER (Special Issue on 1990 Autumn Natl. Conv. IEICE) Category: Integrated Circuits Keyword:
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A Passive TE/TM Mode Splitting Device by the Ion-Exchanged LiNbO₃ Waveguide Yoichi FUJII Hideto HIDAKA
Publication: IEICE TRANSACTIONS (1976-1990) Publication Date: 1985/02/20 Vol. E68-E No. 2 pp. 111-112 Type of Manuscript: LETTER Category: Optical and Quantum Electronics Keyword:
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