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Hideo ITO

Improving Test Coverage by Measuring Path Delay Time Including Transmission Time of FF Wenpo ZHANG Kazuteru NAMBA Hideo ITO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2013/05/01 Vol. E96-D No. 5 pp. 1219-1222 Type of Manuscript: LETTER Category: Dependable Computing Keyword: small delay faults, test coverage, flip-flop, clock pulse,
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FOREWORD Hideo ITOZAKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2013/03/01 Vol. E96-C No. 3 pp. 297-297 Type of Manuscript: FOREWORD Category: Keyword:
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Construction of BILBO FF with Soft-Error-Tolerant Capability Kazuteru NAMBA Hideo ITO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2011/05/01 Vol. E94-D No. 5 pp. 1045-1050 Type of Manuscript: PAPER Category: Dependable Computing Keyword: soft-error-tolerance, DFT (design for test), BISER (built-in soft-error resilience), BILBO (built-in logic block observer), reconfigurable C-element,
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Single-Event-Upset Tolerant RS Flip-Flop with Small Area Kazuteru NAMBA Kengo NAKASHIMA Hideo ITO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/12/01 Vol. E93-D No. 12 pp. 3407-3409 Type of Manuscript: LETTER Category: Dependable Computing Keyword: soft error, single-event-upset (SEU) tolerance, reset-set flip-flop (RS-FF), interlocking feedback loop,
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Analysis of Path Delay Fault Testability for Two-Rail Logic Circuits Kazuteru NAMBA Hideo ITO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/09/01 Vol. E92-A No. 9 pp. 2295-2303 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: two-rail logic circuit, path delay fault, testability, functional sensitizability, over-testing,
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Construction of Soft-Error-Tolerant FF with Wide Error Pulse Detecting Capability Shuangyu RUAN Kazuteru NAMBA Hideo ITO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2009/08/01 Vol. E92-D No. 8 pp. 1534-1541 Type of Manuscript: PAPER Category: Dependable Computing Keyword: soft error, wide pulse, flip-flop, C-element, delay element,
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Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths Kentaroh KATOH Kazuteru NAMBA Hideo ITO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2009/03/01 Vol. E92-D No. 3 pp. 433-442 Type of Manuscript: PAPER Category: Dependable Computing Keyword: dual circuits, master and slave scan paths, delay fault testing, concurrent error detection, DFT,
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Design for Delay Fault Testability of 2-Rail Logic Circuits Kentaroh KATOH Kazuteru NAMBA Hideo ITO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2009/02/01 Vol. E92-D No. 2 pp. 336-341 Type of Manuscript: LETTER Category: Dependable Computing Keyword: 2-rail logic circuits, design for testability, delay fault testing, scan design, set-reset operation,
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Test Compression for Robust Testable Path Delay Fault Testing Using Interleaving and Statistical Coding Kazuteru NAMBA Hideo ITO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2009/02/01 Vol. E92-D No. 2 pp. 269-282 Type of Manuscript: PAPER Category: Dependable Computing Keyword: test compression, statistical coding, run-length coding, delay fault testing, two-pattern testing, scan testing,
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A Checkpointing Method with Small Checkpoint Latency Masato KITAKAMI Bochuan CAI Hideo ITO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2008/03/01 Vol. E91-D No. 3 pp. 857-861 Type of Manuscript: LETTER Category: Dependable Computing Keyword: dependability, checkpointing, checkpoint overhead, checkpoint latency, subcheckpoint,
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Low-Cost IP Core Test Using Tri-Template-Based Codes Gang ZENG Hideo ITO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2007/01/01 Vol. E90-D No. 1 pp. 288-295 Type of Manuscript: PAPER Category: Dependable Computing Keyword: design for testability, IP core testing, test cost reduction, test data compression,
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Redundant Design for Wallace Multiplier Kazuteru NAMBA Hideo ITO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2006/09/01 Vol. E89-D No. 9 pp. 2512-2524 Type of Manuscript: PAPER Category: Dependable Computing Keyword: Wallace multiplier, bit-slice reconfiguration redundant design, defect-tolerance, yield,
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Proposal of Testable Multi-Context FPGA Architecture Kazuteru NAMBA Hideo ITO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2006/05/01 Vol. E89-D No. 5 pp. 1687-1693 Type of Manuscript: PAPER Category: Dependable Computing Keyword: multi-context FPGA, single stuck-at fault, design for testability,
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Concurrent Core Testing for SOC Using Merged Test Set and Scan Tree Gang ZENG Hideo ITO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2006/03/01 Vol. E89-D No. 3 pp. 1157-1164 Type of Manuscript: PAPER Category: Dependable Computing Keyword: concurrent testing, SOC testing, test cost reduction, test data compression,
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Scan Design for Two-Pattern Test without Extra Latches Kazuteru NAMBA Hideo ITO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2005/12/01 Vol. E88-D No. 12 pp. 2777-2785 Type of Manuscript: PAPER Category: Dependable Computing Keyword: two-pattern testing, delay fault testing, scan design, enhanced scan,
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Deterministic Delay Fault BIST Using Adjacency Test Pattern Generation Kazuteru NAMBA Hideo ITO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2005/09/01 Vol. E88-D No. 9 pp. 2135-2142 Type of Manuscript: PAPER Category: Dependable Computing Keyword: two-pattern testing, adjacency test, deterministic test generation, BIST,
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X-Tolerant Test Data Compression for SOC with Enhanced Diagnosis Capability Gang ZENG Hideo ITO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2005/07/01 Vol. E88-D No. 7 pp. 1662-1670 Type of Manuscript: PAPER Category: Dependable Computing Keyword: SOC testing, test cost reduction, test data compression, unknown state, test diagnosis,
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Hybrid Pattern BIST for Low-Cost Core Testing Using Embedded FPGA Core Gang ZENG Hideo ITO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2005/05/01 Vol. E88-D No. 5 pp. 984-992 Type of Manuscript: PAPER Category: Dependable Computing Keyword: hybrid pattern BIST, core testing, test cost reduction, FPGA core, reconfigurable system-on-a-chip,
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Escape and Restoration Routing: Suspensive Deadlock Recovery in Interconnection Networks Toshinori TAKABATAKE Masato KITAKAMI Hideo ITO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2002/05/01 Vol. E85-D No. 5 pp. 824-832 Type of Manuscript: PAPER Category: Computer Systems Keyword: interconnection network, suspensive deadlock recovery, fault-tolerant routing, escape, restoration,
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FOREWORD Hideo ITO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2001/11/01 Vol. E84-D No. 11 pp. 1451-1451 Type of Manuscript: FOREWORD Category: Keyword:
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Fault-Tolerant Routing Algorithms for Hypercube Interconnection Networks Keiichi KANEKO Hideo ITO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2001/01/01 Vol. E84-D No. 1 pp. 121-128 Type of Manuscript: PAPER Category: Fault Tolerance Keyword: hypercube interconnection networks, fault-tolerant routing, full reachability, Hamming distance, communication,
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HCC: Generalized Hierarchical Completely-Connected Networks Toshinori TAKABATAKE Keiichi KANEKO Hideo ITO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2000/06/20 Vol. E83-D No. 6 pp. 1216-1224 Type of Manuscript: PAPER Category: Computer Systems Keyword: interconnection networks, generalized network, hierarchical network, completely-connected network, routing strategy,
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Defect and Fault Tolerance SRAM-Based FPGAs by Shifting the Configuration Data Abderrahim DOUMAR Hideo ITO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2000/05/20 Vol. E83-D No. 5 pp. 1104-1115 Type of Manuscript: PAPER Category: Fault Tolerance Keyword: defect tolerance, fault tolerance, field programmable gate array (FPGA), shifting configurations data, yield improvement,
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Fast Testable Design for SRAM-Based FPGAs Abderrahim DOUMAR Toshiaki OHMAMEUDA Hideo ITO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2000/05/20 Vol. E83-D No. 5 pp. 1116-1127 Type of Manuscript: PAPER Category: Fault Tolerance Keyword: field programmable gate array (FPGA), testing, design for testing, shifting configurations,
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Dynamic Constructive Fault Tolerant Algorithm for Feedforward Neural Networks Nait Charif HAMMADI Toshiaki OHMAMEUDA Keiichi KANEKO Hideo ITO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1998/01/20 Vol. E81-D No. 1 pp. 115-123 Type of Manuscript: PAPER Category: Bio-Cybernetics and Neurocomputing Keyword: feedforward neural network, dynamic constructive algorithm, fault tolerance, DCFTA,
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On the Activation Function and Fault Tolerance in Feedforward Neural Networks Nait Charif HAMMADI Hideo ITO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1998/01/20 Vol. E81-D No. 1 pp. 66-72 Type of Manuscript: PAPER Category: Fault Tolerant Computing Keyword: feedforward neural network, XOR problem, critical weights, fault tolerance, generalization ability,
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Detection of Fine lron Particles in High Speed Scrolled Wire by High-T_c SQUID Hideo ITOZAKI Tatsuoki NAGAISHI Haruhisa TOYODA Hirokazu KUGAI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/10/20 Vol. E80-C No. 10 pp. 1247-1251 Type of Manuscript: INVITED PAPER (Special Issue on Basic Properties and Applications of Superconductive Electron Devices) Category: Keyword: high-T_c SQUID, large washer, flux transformer, nondestructive evaluation,
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Automatic Adjustment of Delay Time and Feedback Gain in Delayed Feedback Control of Chaos Hiroyuki NAKAJIMA Hideo ITO Yoshisuke UEDA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/09/20 Vol. E80-A No. 9 pp. 1554-1559 Type of Manuscript: Special Section PAPER (Special Section on Nonlinear Theory and its Applications) Category: Keyword: chaos, control, delay time, feedback, gradient descent,
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A Learning Algorithm for Fault Tolerant Feedforward Neural Networks Nait Charif HAMMADI Hideo ITO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1997/01/20 Vol. E80-D No. 1 pp. 21-27 Type of Manuscript: Special Section PAPER (Special Issue on Fault-Tolerant Computing) Category: Redundancy Techniques Keyword: feedforward neural network, learning algorithm, relevance of synaptic weights, essential link, open faults,
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High-T_c Superconducting Quantum Interference Device with Additional Positive Feedback Akira ADACHI Ken'ichi OKAJIMA Youichi TAKADA Saburo TANAKA Hideo ITOZAKI Haruhisa TOYODA Hisashi KADO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/05/20 Vol. E78-C No. 5 pp. 519-525 Type of Manuscript: Special Section PAPER (Special Issue on Superconducting Electronics and Its Applications) Category: SQUID sensor and multi-channel SQUID system Keyword: high-T_c dc-SQUID, additional positive feedback, direct offset integration technique, effective flux-to-voltage transfer function, magnetic field noise,
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Multi-Channel SQUID Hisashi KADO Gen UEHARA Hisanao OGATA Hideo ITOZAKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/05/20 Vol. E78-C No. 5 pp. 511-518 Type of Manuscript: INVITED PAPER (Special Issue on Superconducting Electronics and Its Applications) Category: SQUID sensor and multi-channel SQUID system Keyword: SQUID, biomagnetism, ELL, dewar, magnetically shielded room, inverse problem, magnetic source localization,
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Multi-Channel High T_c SQUID Hideo ITOZAKI Saburo TANAKA Tatsuoki NAGAISHI Hisashi KADO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1994/08/20 Vol. E77-C No. 8 pp. 1185-1190 Type of Manuscript: INVITED PAPER (Special Section on Superconducting Devices) Category: HTS Keyword: super conductive electronics, high T_c superconductor, SQUID, step edge junction, biomagnetic signals, magnetocardiogram,
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Interconnection Architecture Based on Beam-Steering Devices Hideo ITOH Seiji MUKAI Hiroyoshi YAJIMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1994/01/20 Vol. E77-C No. 1 pp. 15-22 Type of Manuscript: INVITED PAPER (Special Issue on Optical Interconnection) Category: Keyword: optical interconnection, optical bus, optical link, beam-scanning, fringe-shifting, twin-striped laser diode,
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Array Structure Using Basic Wiring Channels for WSI Hypercube Hideo ITO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1992/11/20 Vol. E75-D No. 6 pp. 884-893 Type of Manuscript: PAPER Category: Fault Tolerant Computing Keyword: wafer-scale integration, hypercube, array, basic channel, defect,
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A 2-Rail Logic Combinational Circuit for Easy Detection of Stuck-Open and Stuck-On Faults in FETs Hideo ITO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1992/11/20 Vol. E75-D No. 6 pp. 894-901 Type of Manuscript: PAPER Category: Fault Tolerant Computing Keyword: easily testable design, CMOS, stuck-open fault, stuck-on fault, 2-rail logic,
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High T_c Superconducting Microwave Passive Components Kenjiro HIGAKI Hideo ITOZAKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1992/08/20 Vol. E75-C No. 8 pp. 883-887 Type of Manuscript: Special Section PAPER (Special Issue on Cryogenic Microwave Devices) Category: Passive Devices Keyword: high T_c superconductor, superconducting microwave component,
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Large Scale Rectangular Grids in Hypercubes: An Embedding Scheme and Its Evaluation M. A. Amaral HENRIQUES Hideo ITO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1991/06/20 Vol. E74-D No. 6 pp. 1705-1714 Type of Manuscript: PAPER Category: Software Systems Keyword:
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Self-Checking Checker Designs for Various 2-Rail Codes Hideo ITOH Matsuroh NAKAMICHI
Publication: IEICE TRANSACTIONS (1976-1990) Publication Date: 1982/11/20 Vol. E65-E No. 11 pp. 665-671 Type of Manuscript: PAPER Category: Digital Circuits Keyword:
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