Hideo FUJIWARA


Realization of SR-Equivalents Using Generalized Shift Registers for Secure Scan Design
Hideo FUJIWARA Katsuya FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/08/01
Vol. E99-D  No. 8  pp. 2182-2185
Type of Manuscript:  LETTER
Category: Dependable Computing
Keyword: 
design-for-testabilityscan designgeneralized feedback/feed-forward shift registerssecurityscan-based side-channel attack
 Summary | Full Text:PDF(399.6KB)

Properties of Generalized Feedback Shift Registers for Secure Scan Design
Hideo FUJIWARA Katsuya FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/04/01
Vol. E99-D  No. 4  pp. 1255-1258
Type of Manuscript:  LETTER
Category: Dependable Computing
Keyword: 
design-for-testabilityscan designgeneralized feedback/feed-forward shift registerssecurityscan-based side-channel attack
 Summary | Full Text:PDF(395.2KB)

Strongly Secure Scan Design Using Generalized Feed Forward Shift Registers
Hideo FUJIWARA Katsuya FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2015/10/01
Vol. E98-D  No. 10  pp. 1852-1855
Type of Manuscript:  LETTER
Category: Dependable Computing
Keyword: 
design-for-testabilityscan designgeneralized feed-forward shift registerssecurityscan-based side-channel attack
 Summary | Full Text:PDF(352.9KB)

Generalized Feed Forward Shift Registers and Their Application to Secure Scan Design
Katsuya FUJIWARA Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/05/01
Vol. E96-D  No. 5  pp. 1125-1133
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
design-for-testabilityscan designshift register equivalentsshift register quasi-equivalentsgeneralized feed-forward shift registerssecurityscan-based side-channel attack
 Summary | Full Text:PDF(1.7MB)

Test Pattern Ordering and Selection for High Quality Test Set under Constraints
Michiko INOUE Akira TAKETANI Tomokazu YONEDA Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/12/01
Vol. E95-D  No. 12  pp. 3001-3009
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
small delay defectsSDQLATPG
 Summary | Full Text:PDF(850.8KB)

Differential Behavior Equivalent Classes of Shift Register Equivalents for Secure and Testable Scan Design
Katsuya FUJIWARA Hideo FUJIWARA Hideo TAMAMOTO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/07/01
Vol. E94-D  No. 7  pp. 1430-1439
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
design-for-testabilityscan designshift register equivalentssecurityscan-based side-channel attack
 Summary | Full Text:PDF(599.1KB)

F-Scan: A DFT Method for Functional Scan at RTL
Marie Engelene J. OBIEN Satoshi OHTAKE Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/01/01
Vol. E94-D  No. 1  pp. 104-113
Type of Manuscript:  PAPER
Category: Information Network
Keyword: 
scan-based DFTfunctional RTL circuitshigh-level testingassignment decision diagrams
 Summary | Full Text:PDF(700.9KB)

A Method of Path Mapping from RTL to Gate Level and Its Application to False Path Identification
Hiroshi IWATA Satoshi OHTAKE Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/07/01
Vol. E93-D  No. 7  pp. 1857-1865
Type of Manuscript:  PAPER
Category: Information Network
Keyword: 
false pathhigh level testingpath mappingfunctional equivalence
 Summary | Full Text:PDF(348.9KB)

Design and Optimization of Transparency-Based TAM for SoC Test
Tomokazu YONEDA Akiko SHUTO Hideyuki ICHIHARA Tomoo INOUE Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/06/01
Vol. E93-D  No. 6  pp. 1549-1559
Type of Manuscript:  PAPER
Category: Information Network
Keyword: 
SoC testdesign for testabilityTAM designtransparencyILP
 Summary | Full Text:PDF(563.8KB)

A Fault Dependent Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint
Ryoichi INOUE Toshinori HOSOKAWA Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/01/01
Vol. E93-D  No. 1  pp. 24-32
Type of Manuscript:  Special Section PAPER (Special Section on Test, Diagnosis and Verification of SOCs)
Category: 
Keyword: 
state-observable FSMslogical fault testingtiming fault testingfault sensitization coveragen-detection
 Summary | Full Text:PDF(2.1MB)

Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips
Thomas Edison YU Tomokazu YONEDA Krishnendu CHAKRABARTY Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/10/01
Vol. E91-D  No. 10  pp. 2440-2448
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
SoC testingtest architecture designtest schedulingthermal constraint
 Summary | Full Text:PDF(687.1KB)

NoC-Compatible Wrapper Design and Optimization under Channel-Bandwidth and Test-Time Constraints
Fawnizu Azmadi HUSSIN Tomokazu YONEDA Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/07/01
Vol. E91-D  No. 7  pp. 2008-2017
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
SoC testingNoC testingtest wrapper designNoC-compatible wrapper
 Summary | Full Text:PDF(950.4KB)

On NoC Bandwidth Sharing for the Optimization of Area Cost and Test Application Time
Fawnizu Azmadi HUSSIN Tomokazu YONEDA Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/07/01
Vol. E91-D  No. 7  pp. 1999-2007
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
SoC test schedulingtest wrappertest access mechanismNoC-reusebandwidth sharing
 Summary | Full Text:PDF(922.6KB)

Scheduling Power-Constrained Tests through the SoC Functional Bus
Fawnizu Azmadi HUSSIN Tomokazu YONEDA Alex ORAILOLU Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/03/01
Vol. E91-D  No. 3  pp. 736-746
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSIs)
Category: High-Level Testing
Keyword: 
functional busfunctional TAMpower-constrainedpacket-based schedulingsystem-on-chip testing
 Summary | Full Text:PDF(810.6KB)

Effective Domain Partitioning for Multi-Clock Domain IP Core Wrapper Design under Power Constraints
Thomas Edison YU Tomokazu YONEDA Danella ZHAO Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/03/01
Vol. E91-D  No. 3  pp. 807-814
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
multi-clock domainwrapper designSoCembedded core testtest scheduling
 Summary | Full Text:PDF(796.2KB)

Design for Testability Method to Avoid Error Masking of Software-Based Self-Test for Processors
Masato NAKAZATO Michiko INOUE Satoshi OHTAKE Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/03/01
Vol. E91-D  No. 3  pp. 763-770
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSIs)
Category: High-Level Testing
Keyword: 
software-based self-testprocessortest program templatedesign for testabilityerror maskingat-speed testing
 Summary | Full Text:PDF(522.6KB)

Test Scheduling for Multi-Clock Domain SoCs under Power Constraint
Tomokazu YONEDA Kimihiko MASUDA Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/03/01
Vol. E91-D  No. 3  pp. 747-755
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSIs)
Category: High-Level Testing
Keyword: 
multi-clock domain SoCtest schedulingtest access mechanismpower consumption
 Summary | Full Text:PDF(345.3KB)

Analysis of Test Generation Complexity for Stuck-At and Path Delay Faults Based on τk-Notation
Chia Yee OOI Thomas CLOUQUEUR Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/08/01
Vol. E90-D  No. 8  pp. 1202-1212
Type of Manuscript:  PAPER
Category: Complexity Theory
Keyword: 
easily testablestuck-at faultspath delay faultstest generation complexity
 Summary | Full Text:PDF(367.4KB)

Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability
Masato NAKAZATO Satoshi OHTAKE Kewal K. SALUJA Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/01/01
Vol. E90-D  No. 1  pp. 296-305
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
sequential circuittest generationsynthesis for testabilityfinite state machinetest knowledge
 Summary | Full Text:PDF(641.6KB)

Effect of BIST Pretest on IC Defect Level
Yoshiyuki NAKAMURA Jacob SAVIR Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/10/01
Vol. E89-D  No. 10  pp. 2626-2636
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
BISTfault coveragedefect level
 Summary | Full Text:PDF(1.2MB)

A Low Power Deterministic Test Using Scan Chain Disable Technique
Zhiqiang YOU Tsuyoshi IWAGAKI Michiko INOUE Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/06/01
Vol. E89-D  No. 6  pp. 1931-1939
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
low power testingfull scan testingdeterministic testscan chain disabletabu search algorithm
 Summary | Full Text:PDF(638.3KB)

A Memory Grouping Method for Reducing Memory BIST Logic of System-on-Chips
Masahide MIYAZAKI Tomokazu YONEDA Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/04/01
Vol. E89-D  No. 4  pp. 1490-1497
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
SoCtest schedulingwrapperdesign for testmemory BIST
 Summary | Full Text:PDF(1MB)

Error Identification in At-Speed Scan BIST Environment in the Presence of Circuit and Tester Speed Mismatch
Yoshiyuki NAKAMURA Thomas CLOUQUEUR Kewal K. SALUJA Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/03/01
Vol. E89-D  No. 3  pp. 1165-1172
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
BISTfault diagnosiserror identificationat-speed testlow speed tester
 Summary | Full Text:PDF(462.4KB)

Classification of Sequential Circuits Based on τk Notation and Its Applications
Chia Yee OOI Thomas CLOUQUEUR Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/12/01
Vol. E88-D  No. 12  pp. 2738-2747
Type of Manuscript:  PAPER
Category: VLSI Systems
Keyword: 
test generationeasily testable sequential circuitscomplexitydesign for testabilitysynthesis for testability
 Summary | Full Text:PDF(391.4KB)

Power-Constrained Test Synthesis and Scheduling Algorithms for Non-Scan BIST-able RTL Data Paths
Zhiqiang YOU Ken'ichi YAMAGUCHI Michiko INOUE Jacob SAVIR Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/08/01
Vol. E88-D  No. 8  pp. 1940-1947
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
design for testabilityRTL data pathbuilt-in self-testlow power testingtest scheduling
 Summary | Full Text:PDF(447.5KB)

Defect Level vs. Yield and Fault Coverage in the Presence of an Unreliable BIST
Yoshiyuki NAKAMURA Jacob SAVIR Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/06/01
Vol. E88-D  No. 6  pp. 1210-1216
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
BISTfault coveragedefect level
 Summary | Full Text:PDF(629.9KB)

Delay Fault Testing of Processor Cores in Functional Mode
Virendra SINGH Michiko INOUE Kewal K. SALUJA Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/03/01
Vol. E88-D  No. 3  pp. 610-618
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
processor testdelay fault testingsoftware-based self-testat-speed test
 Summary | Full Text:PDF(331.2KB)

A Design Scheme for Delay Testing of Controllers Using State Transition Information
Tsuyoshi IWAGAKI Satoshi OHTAKE Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12  pp. 3200-3207
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Test
Keyword: 
controllerdelay faultnon-scan designinvalid test state and transition generatorat-speed test
 Summary | Full Text:PDF(463.8KB)

Preemptive System-on-Chip Test Scheduling
Erik LARSSON Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/03/01
Vol. E87-D  No. 3  pp. 620-629
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSI)
Category: SoC Testing
Keyword: 
test schedulingtest access mechanism designpreemptive schedulingsystem-on-chip testing
 Summary | Full Text:PDF(3.2MB)

A DFT Selection Method for Reducing Test Application Time of System-on-Chips
Masahide MIYAZAKI Toshinori HOSOKAWA Hiroshi DATE Michiaki MURAOKA Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/03/01
Vol. E87-D  No. 3  pp. 609-619
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSI)
Category: SoC Testing
Keyword: 
test schedulingtest access mechanismwrapperdesign for test
 Summary | Full Text:PDF(2.2MB)

A Test Plan Grouping Method to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint
Toshinori HOSOKAWA Hiroshi DATE Masahide MIYAZAKI Michiaki MURAOKA Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/12/01
Vol. E86-D  No. 12  pp. 2674-2683
Type of Manuscript:  Special Section PAPER (Special Issue on Dependable Computing)
Category: Test
Keyword: 
test plan groupingtest controllerspartly compacted test plan tablesRTL data pathshierarchical test generation
 Summary | Full Text:PDF(1.1MB)

Non-scan Design for Testability for Synchronous Sequential Circuits Based on Fault-Oriented Conflict Analysis
Dong XIANG Shan GU Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/11/01
Vol. E86-D  No. 11  pp. 2407-2417
Type of Manuscript:  PAPER
Category: Fault Tolerance
Keyword: 
at-speed testconflictcontaining assignmentnon-scan design for testabilitysequential depth for testability
 Summary | Full Text:PDF(1.2MB)

Design for Two-Pattern Testability of Controller-Data Path Circuits
Md. ALTAF-UL-AMIN Satoshi OHTAKE Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/06/01
Vol. E86-D  No. 6  pp. 1042-1050
Type of Manuscript:  PAPER
Category: Fault Tolerance
Keyword: 
design for testabilityhierarchical testabilitydelay testingcontroller-data path circuittwo-pattern testability
 Summary | Full Text:PDF(1.3MB)

Design for Hierarchical Two-Pattern Testability of Data Paths
Md. Altaf-Ul-AMIN Satoshi OHTAKE Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/06/01
Vol. E85-D  No. 6  pp. 975-984
Type of Manuscript:  PAPER
Category: Fault Tolerance
Keyword: 
design for testabilitydelay testinghierarchical testabilitytwo-pattern testability
 Summary | Full Text:PDF(1.1MB)

Fault-Tolerant and Self-Stabilizing Protocols Using an Unreliable Failure Detector
Hiroyoshi MATSUI Michiko INOUE Toshimitsu MASUZAWA Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2000/10/25
Vol. E83-D  No. 10  pp. 1831-1840
Type of Manuscript:  PAPER
Category: Algorithms
Keyword: 
distributed algorithmsself-stabilizationfault-tolerancefailure detectorx-group consensus
 Summary | Full Text:PDF(514.1KB)

Wait-Free Linearizable Distributed Shared Memory
Sen MORIYA Katsuro SUDA Michiko INOUE Toshimitsu MASUZAWA Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2000/08/25
Vol. E83-D  No. 8  pp. 1611-1621
Type of Manuscript:  PAPER
Category: Algorithms
Keyword: 
synchronous message-passing systemdistributed shared memorylinearizabilitywait-freedom
 Summary | Full Text:PDF(658.2KB)

Parallel Algorithms for the All Nearest Neighbors of Binary Image on the BSP Model
Takashi ISHIMIZU Akihiro FUJIWARA Michiko INOUE Toshimitsu MASUZAWA Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2000/02/25
Vol. E83-D  No. 2  pp. 151-158
Type of Manuscript:  PAPER
Category: Algorithms
Keyword: 
parallel algorithmBSP modelall nearest neighbors
 Summary | Full Text:PDF(642.8KB)

Testing for the Programming Circuit of SRAM-Based FPGAs
Hiroyuki MICHINISHI Tokumi YOKOHIRA Takuji OKAMOTO Tomoo INOUE Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/06/25
Vol. E82-D  No. 6  pp. 1051-1057
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
fault detectionLUT-based FPGASRAM-based FPGAfunctional faultconfiguration
 Summary | Full Text:PDF(608.4KB)

High-Level Synthesis for Weakly Testable Data Paths
Michiko INOUE Kenji NODA Takeshi HIGASHIMURA Toshimitsu MASUZAWA Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/07/25
Vol. E81-D  No. 7  pp. 645-653
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Diagnosis of VLSI)
Category: Test Synthesis
Keyword: 
high-level synthesistestabilitysequential ATPGnon-scan design
 Summary | Full Text:PDF(894.6KB)

Performance Analysis of Parallel Test Generation for Combinational Circuits
Tomoo INOUE Takaharu FUJII Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/09/25
Vol. E79-D  No. 9  pp. 1257-1265
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
test generationparallel processingperformance analysisinterprocessor communicationspeedup
 Summary | Full Text:PDF(723KB)

On the Effect of Scheduling in Test Generation
Tomoo INOUE Hironori MAEDA Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/08/25
Vol. E79-D  No. 8  pp. 1190-1197
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
test generationtest generation schedulefault orderingfault dominancecost of testing
 Summary | Full Text:PDF(654.7KB)

A Simple Parallel Algorithm for the Medial Axis Transform
Akihiro FUJIWARA Michiko INOUE Toshimitsu MASUZAWA Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/08/25
Vol. E79-D  No. 8  pp. 1038-1045
Type of Manuscript:  Special Section PAPER (Special Issue on Architectures, Algorithms and Networks for Massively Parallel Computing)
Category: Algorithms
Keyword: 
parallel algorithmimage processingmedial axis transformPRAMmeshhypercube
 Summary | Full Text:PDF(637.4KB)

FOREWORD
Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/07/25
Vol. E78-D  No. 7  pp. 789-790
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF(93.3KB)

Fault Detection Capability of an O (m・n) Test Generation Algorithm for PLAs
Yinghua MIN Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1991/10/25
Vol. E74-D  No. 10  pp. 3506-3512
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
 Summary | Full Text:PDF(485.6KB)

FOREWORD
Makoto NAGAO Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1991/01/25
Vol. E74-D  No. 1  pp. 177-178
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF(142.1KB)

Fast Test Pattern Generation Using a Multiprocessor System
Hideo FUJIWARA Akira MOTOHARA 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1988/04/25
Vol. E71-E  No. 4  pp. 441-447
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
 Summary | Full Text:PDF(503.1KB)