Hidenori GYOTEN


Area Efficient Annealing Processor for Ising Model without Random Number Generator
Hidenori GYOTEN Masayuki HIROMOTO Takashi SATO 
Publication:   
Publication Date: 2018/02/01
Vol. E101-D  No. 2  pp. 314-323
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Device and Architecture
Keyword: 
combinatorial optimization problemmax-cut problemIsing modelannealingFPGA
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