Hideki KITADA


Evaluation of Temperature Dependence of Local Stress and CMOS Circuit Properties in Three-Dimensional LSI Design
Shoichi MIYAHARA Hideki KITADA Hiroko TASHIRO Aki DOTE Seiki SAKUYAMA 
Publication:   - - Abstracts of (Japanese Edition)
Publication Date: 2018/02/01
Vol. J101-C  No. 2  pp. 74-82
Type of Manuscript:  Special Section PAPER (Special Section on Heterogeneous Integration Packaging Technologies Realizing Next Generation Mobility Devices)
Category: 
Keyword: 
3D-LSICMOS propertyTSV stresstemperature dependence
 Summary | Full Text(in Japanese):PDF(1.2MB)

3D Large Scale Integration Technology Using Wafer-on-Wafer (WOW) Stacking
Takayuki OHBA Nobuhide MAEDA Hideki KITADA Koji FUJIMOTO Akihito KAWAI Kazuhisa ARAI Kosuke SUZUKI Tomoji NAKAMURA 
Publication:   C - Abstracts of IEICE TRANSACTIONS on Electronics (Japanese Edition)
Publication Date: 2010/11/01
Vol. J93-C  No. 11  pp. 464-476
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Packaging and Its Related Topics about Evaluation and Analysis Technologies for High-Density Packaging)
Category: 
Keyword: 
wafer stackingWOWthinningTSVhigh density integrationdie yield
 Summary | Full Text(in Japanese):PDF(3.7MB)