Hideki ASAI


FOREWORD
Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/03/01
Vol. E97-A  No. 3  pp. 725-725
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF(205.8KB)

An Approach for Practical Use of Common-Mode Noise Reduction Technique for In-Vehicle Electronic Equipment
Takanori UNO Kouji ICHIKAWA Yuichi MABUCHI Atsushi NAKAMURA Yuji OKAZAKI Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2010/07/01
Vol. E93-B  No. 7  pp. 1788-1796
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Electromagnetic Compatibility Technology in Conjunction with Main Topics of EMC'09/Kyoto)
Category: Transmission Lines and Cables
Keyword: 
EMIcommon-mode currentoptimization algorithmECU
 Summary | Full Text:PDF(2MB)

An Optimization System with Parallel Processing for Reducing Common-Mode Current on Electronic Control Unit
Yuji OKAZAKI Takanori UNO Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/06/01
Vol. E93-C  No. 6  pp. 827-834
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
EMIcommon-mode currentoptimization algorithmECUparallel processing
 Summary | Full Text:PDF(9MB)

CMOS Circuit Simulation Using Latency Insertion Method
Tadatoshi SEKINE Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/10/01
Vol. E92-A  No. 10  pp. 2546-2553
Type of Manuscript:  Special Section PAPER (Special Section on Nonlinear Theory and its Applications)
Category: Nonlinear Problems
Keyword: 
latency insertion methodCMOS circuitfast circuit simulation
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Fast Simulation Technique of Plane Circuits via Two-Layer CNN-Based Modeling
Yuichi TANJI Hideki ASAI Masayoshi ODA Yoshifumi NISHIO Akio USHIDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12  pp. 3757-3762
Type of Manuscript:  PAPER
Category: Nonlinear Problems
Keyword: 
cellular neural networksplane circuitssignal/power integrityleapfrog method
 Summary | Full Text:PDF(456.7KB)

Matrix Order Reduction by Nodal Analysis Formulation and Relaxation-Based Fast Simulation for Power/Ground Plane
Tadatoshi SEKINE Yuichi TANJI Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/09/01
Vol. E91-A  No. 9  pp. 2450-2455
Type of Manuscript:  Special Section PAPER (Special Section on Nonlinear Theory and its Applications)
Category: Analysis, Modelng and Simulation
Keyword: 
matrix order reductionnodal analysis methodrelaxation methodplane networks
 Summary | Full Text:PDF(301.8KB)

Acceleration of ADI-FDTD Method by Gauss-Seidel Relaxation Approach
Yuya NAKAZONO Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/02/01
Vol. E91-A  No. 2  pp. 550-553
Type of Manuscript:  Special Section LETTER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
electromagnetic field analysisADI-FDTD methodrelaxation method2-D simulation
 Summary | Full Text:PDF(352.9KB)

Fast Transient Simulation of Power Distribution Networks Containing Dispersion Based on Parallel-Distributed Leapfrog Algorithm
Takayuki WATANABE Yuichi TANJI Hidemasa KUBOTA Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/02/01
Vol. E90-A  No. 2  pp. 388-397
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
circuit simulationpower integrityleapfrog algorithmfrequency-dependent dispersionparallel computation
 Summary | Full Text:PDF(940.8KB)

An Enhanced Time-Domain Circuit Simulation Technique Based on LIM
Hidemasa KUBOTA Yuichi TANJI Takayuki WATANABE Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/05/01
Vol. E89-A  No. 5  pp. 1505-1506
Type of Manuscript:  LETTER
Category: Numerical Analysis and Optimization
Keyword: 
circuit simulationLIMnumerical integrationpower integritysignal integrity
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New Criteria of Selective Orthogonal Matrix Least-Squares Method for Macromodeling Multiport Networks Characterized by Sampled Data
Yuichi TANJI Masaya SUZUKI Takayuki WATANABE Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/02/01
Vol. E88-A  No. 2  pp. 524-532
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
top-down design and bottom-up verification methodologyorthogonal least-squares methodVerilog-AMSVerilog-Asampled datamatrix rational approximation
 Summary | Full Text:PDF(506.7KB)

An Efficient Simulation Method of Linear/Nonlinear Mixed Circuits Based on Hybrid Model Order Reduction Technique
Takashi MINE Hidemasa KUBOTA Atsushi KAMO Takayuki WATANABE Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/09/01
Vol. E87-A  No. 9  pp. 2274-2279
Type of Manuscript:  Special Section PAPER (Special Section on Nonlinear Theory and its Applications)
Category: 
Keyword: 
circuit simulationcongruence transformationnonlinear circuit reduction technique
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Macromodel Generation for Hybrid Systems Consisting of Electromagnetic Systems and Lumped RLC Circuits Based on Model Order Reduction
Takayuki WATANABE Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/02/01
Vol. E87-A  No. 2  pp. 398-405
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
circuit simulationmodel order reductionfinite-difference frequency domain methodefficient nodal order reduction
 Summary | Full Text:PDF(1.9MB)

Face Image Recognition by 2-Dimensional Discrete Walsh Transform and Multi-Layer Neural Network
Masahiro YOSHIDA Takeshi KAMIO Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/10/01
Vol. E86-A  No. 10  pp. 2623-2627
Type of Manuscript:  Special Section LETTER (Special Section on Information Theory and Its Applications)
Category: Source Coding/Image Processing
Keyword: 
face image recognition2-dimensional discrete Walsh transformneural network
 Summary | Full Text:PDF(181KB)

A Low Voltage Floating Resistor Circuit Having Both Positive and Negative Resistance Values
Shashidhar TANTRY Yasuyuki HIRAKU Takao OURA Teru YONEYAMA Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/02/01
Vol. E86-A  No. 2  pp. 335-341
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
floating resistorpositive-negative resistorlow voltage circuits
 Summary | Full Text:PDF(811.1KB)

A Framework for Macromodeling and Mixed-Mode Simulation of Circuits/Interconnects and Electromagnetic Radiations
Takayuki WATANABE Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/02/01
Vol. E86-A  No. 2  pp. 252-261
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
analog circuit simulationSPICE macromodelelectromagnetic radiationsfinite-difference time-domain method
 Summary | Full Text:PDF(935.8KB)

An Efficient Simulator for Multiport Interconnects with Model Order Reduction Technique
Hidemasa KUBOTA Atsushi KAMO Takayuki WATANABE Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/06/01
Vol. E85-A  No. 6  pp. 1214-1219
Type of Manuscript:  Special Section PAPER (Special Section on Papers Selected from 2001 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2001))
Category: 
Keyword: 
reduced-order modelPRIMAPCB simulationASSISTvoltage controlled current source model
 Summary | Full Text:PDF(931.9KB)

Design and Simulation of 4Q-Multiplier Using Linear and Saturation Regions of MOSFET Complementally
Tsutomu SUZUKI Takao OURA Teru YONEYAMA Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/06/01
Vol. E85-A  No. 6  pp. 1242-1248
Type of Manuscript:  Special Section PAPER (Special Section on Papers Selected from 2001 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2001))
Category: 
Keyword: 
4Q-MultiplierMOSFETlinear regionsaturation regionanalog circuit
 Summary | Full Text:PDF(642.3KB)

A Novel Application of Verilog-A to Modeling and Simulation of High-Speed Interconnects in Time/Frequency Transform-Domain
Kenichi SUZUKI Mitsuhiro TAKEDA Atsushi KAMO Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/02/01
Vol. E85-A  No. 2  pp. 395-398
Type of Manuscript:  Special Section LETTER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
analog-HDLVerilog-Acircuit simulationinterconnects simulationtime/frequency transform-domain
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A CMOS Floating Resistor Circuit Having Both Positive and Negative Resistance Values
Takao OURA Teru YONEYAMA Shashidhar TANTRY Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/02/01
Vol. E85-A  No. 2  pp. 399-402
Type of Manuscript:  Special Section LETTER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
floating resistorMOS resistoranalog electronic circuits
 Summary | Full Text:PDF(264.6KB)

A New Methodology for Optimal Placement of Decoupling Capacitors on Printed Circuit Board
Atsushi KAMO Takayuki WATANABE Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/12/01
Vol. E84-A  No. 12  pp. 3177-3181
Type of Manuscript:  LETTER
Category: Circuit Theory
Keyword: 
Krylov-subspace techniquepartial element equivalent circuit (PEEC)network reductiondecoupling capacitor
 Summary | Full Text:PDF(909.8KB)

Design Method of Neural Networks for Limit Cycle Generator by Linear Programming
Teru YONEYAMA Hiroshi NINOMIYA Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/02/01
Vol. E84-A  No. 2  pp. 688-692
Type of Manuscript:  LETTER
Category: Neural Networks and Bioengineering
Keyword: 
neural networklimit cycle generatorlinear programmingsynaptic weightsanalog electronic circuits
 Summary | Full Text:PDF(262.9KB)

Acceleration Techniques for Synthesis and Analysis of Time-Domain Models of Interconnects Using FDTD Method
Takayuki WATANABE Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/01/01
Vol. E84-A  No. 1  pp. 367-371
Type of Manuscript:  LETTER
Category: Circuit Theory
Keyword: 
circuit simulationFDTD methodtime-domain macromodelcharacteristic impedance
 Summary | Full Text:PDF(258.7KB)

Transient Analysis for Transmission Line Networks Using Expanded GMC
Atsushi KAMO Takayuki WATANABE Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/09/25
Vol. E82-A  No. 9  pp. 1789-1795
Type of Manuscript:  Special Section PAPER (Special Section on Nonlinear Theory and Its Applications)
Category: 
Keyword: 
expanded generalized method of characteristiclinear subcircuitcharacteristic impedancewave propagation function
 Summary | Full Text:PDF(1MB)

A Fast Neural Network Simulator for State Transition Analysis
Atsushi KAMO Hiroshi NINOMIYA Teru YONEYAMA Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/09/25
Vol. E82-A  No. 9  pp. 1796-1801
Type of Manuscript:  Special Section PAPER (Special Section on Nonlinear Theory and Its Applications)
Category: 
Keyword: 
stepwise constant methodmultivalued neural networkASSISTstate transition analysis
 Summary | Full Text:PDF(1.1MB)

Sparsely Interconnected Neural Networks for Associative Memories Applying Discrete Walsh Transform
Takeshi KAMIO Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/03/25
Vol. E82-A  No. 3  pp. 495-499
Type of Manuscript:  Special Section LETTER (Special Section on Selected Papers from the 11th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
sparsely interconnected neural networkassociative memory2-dimensional discrete Walsh transformisolated cells problem
 Summary | Full Text:PDF(212.6KB)

A Fast Algorithm for Spatiotemporal Pattern Analysis of Neural Networks with Multivalued Logic
Hiroshi NINOMIYA Atsushi KAMO Teru YONEYAMA Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/09/25
Vol. E81-A  No. 9  pp. 1847-1852
Type of Manuscript:  Special Section PAPER (Special Section on Nonlinear Theory and Its Applications)
Category: Neural Networks
Keyword: 
continuous-time neural networksmultivalued logicstepwise constant functionspatiotemporal pattern analysis
 Summary | Full Text:PDF(488.5KB)

Relaxation-Based Transient Analysis of Lossy Coupled Transmission Lines Circuits Using Delay Evaluation Technique
Takayuki WATANABE Atsushi KAMO Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/06/25
Vol. E81-A  No. 6  pp. 1055-1062
Type of Manuscript:  Special Section PAPER (Special Section of Papers Selected from ITC-CSCC'97)
Category: Modeling and Simulation
Keyword: 
circuit simulationlossy transmission lineswaveform relaxationdelay evaluation technique
 Summary | Full Text:PDF(613.6KB)

A Neuro-Based Optimization Algorithm for Rectangular Puzzles
Hiroyuki YAMAMOTO Hiroshi NINOMIYA Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/06/25
Vol. E81-A  No. 6  pp. 1113-1118
Type of Manuscript:  Special Section PAPER (Special Section of Papers Selected from ITC-CSCC'97)
Category: Neural Networks
Keyword: 
cubic puzzlestiling problem3-D neuro arrayanalog neural network
 Summary | Full Text:PDF(448.3KB)

A Neuro-Based Optimization Algorithm for Three Dimensional Cylindric Puzzles
Hiroyuki YAMAMOTO Takeshi NAKAYAMA Hiroshi NINOMIYA Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/06/25
Vol. E80-A  No. 6  pp. 1049-1054
Type of Manuscript:  Special Section PAPER (Special Section of Papers Selected from 1996 International Technical Conference on Circuits/Systems, Computers and Communications(ITC-CSCC'96))
Category: 
Keyword: 
cylindrical puzzlestiling problempolyominoanalog neural networkomega function heuristic
 Summary | Full Text:PDF(456.2KB)

Acceleration Techniques for Waveform Relaxation Approaches to Coupled Lossy Transmission Lines Circuit Analysis Using GMC and GLDW Techniques
Takayuki WATANABE Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/10/25
Vol. E79-A  No. 10  pp. 1538-1545
Type of Manuscript:  Special Section PAPER (Special Section on Nonlinear Theory and its Applications (NOLTA))
Category: Nonlinear Circuits and Bifurcation
Keyword: 
lossy transmission linegeneralized method of characteristicswaveform relaxation methodline delay partitioning techniquecircuit simulator
 Summary | Full Text:PDF(624.7KB)

Neural Networks for Digital Sequential Circuits
Hiroshi NINOMIYA Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/12/25
Vol. E77-A  No. 12  pp. 2112-2115
Type of Manuscript:  LETTER
Category: Neural Networks
Keyword: 
Hopfield neural networksoptimization problemdigital sequential circuitsenergy functionglobal convergence
 Summary | Full Text:PDF(218.2KB)

Efficient Simulation of Lossy Coupled Transmission Lines by the Application of Window Partitioning Technique to the Waveform Relaxation Approach
Vijaya Gopal BANDI Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/11/25
Vol. E77-A  No. 11  pp. 1742-1752
Type of Manuscript:  Special Section PAPER (Special Section on Nonlinear Theory and Its Applications)
Category: Analysis of Nonlinear Circuits and Systems
Keyword: 
transient analysiscoupled lossy interconnectscharacteristic modelwaveform relaxationtransformation matrixline delay window partitioningcharacteristic impedanceexponential propagation function
 Summary | Full Text:PDF(771.3KB)

A Neural Net Approach to Discrete Walsh Transform
Takeshi KAMIO Hiroshi NINOMIYA Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/11/25
Vol. E77-A  No. 11  pp. 1882-1886
Type of Manuscript:  Special Section LETTER (Special Section of Letters Selected from the 1994 IEICE Spring Conference)
Category: 
Keyword: 
neural networklinear programming problemenergy functiondiscrete Walsh transformWalsh functionHadamard matrix
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Design and Simulation of Neural Network Digital Sequential Circuits
Hiroshi NINOMIYA Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/06/25
Vol. E77-A  No. 6  pp. 968-976
Type of Manuscript:  Special Section PAPER (Special Section of Papers Selected from 1993 Joint Technical Conference on Circuits/Systems, Computers and Communications (JTC-CSCC'93))
Category: Analog Circuits and Signal Processing
Keyword: 
Hopfield neural networksoptimization problemdigital sequential circuitsenergy functionglobal convergence
 Summary | Full Text:PDF(449.3KB)

Dynamically Overlapped Partitioning Technique to Implement Waveform Relaxation Simulation of Bipolar Circuits
Vijaya Gopal BANDI Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/06/25
Vol. E77-A  No. 6  pp. 1080-1084
Type of Manuscript:  LETTER
Category: Nonlinear Circuits and Systems
Keyword: 
circuit simulationweveform relaxationoverlapped partitioningsensitivity criteriawaveform latency
 Summary | Full Text:PDF(318.9KB)

Relaxation-Based Algorithms for Bipolar Circuit Analysis
Masaki ISHIDA Koichi HAYASHI Masakatsu NISHIGAKI Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/06/25
Vol. E77-A  No. 6  pp. 1023-1027
Type of Manuscript:  Special Section PAPER (Special Section of Papers Selected from 1993 Joint Technical Conference on Circuits/Systems, Computers and Communications (JTC-CSCC'93))
Category: Modeling and Simulation
Keyword: 
circuit simulationdynamic partitioningITAwaveform relaxationbipolar circit
 Summary | Full Text:PDF(340.3KB)

Mixed Mode Circuit Simulation Using Dynamic Network Separation and Selective Trace
Masakatsu NISHIGAKI Nobuyuki TANAKA Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/03/25
Vol. E77-A  No. 3  pp. 454-460
Type of Manuscript:  Special Section PAPER (Special Section on the 6th Karuizawa Workshop on Circuits and Systems)
Category: Modeling and Simulation
Keyword: 
mixed mode circuit simulationdynamic partitioningnetwork separationlatencyselective trace
 Summary | Full Text:PDF(528.9KB)

Acceleration Techniques for Waveform Relaxation Analysis of RLCG Transmission Lines Driven by Bipolar Logic Gates
Vijaya Gopal BANDI Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/09/25
Vol. E76-A  No. 9  pp. 1527-1534
Type of Manuscript:  PAPER
Category: Nonlinear Circuits and Systems
Keyword: 
circuit simulationwaveform relaxationlossy transmission linesmethod of characteristicslumped element modelwaveform latency
 Summary | Full Text:PDF(538.8KB)

A Waveform Relaxation Method Applicable to the Simulation of ECL Circuits with Gate Level Partitioning
Vijaya Gopal BANDI Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/04/25
Vol. E76-A  No. 4  pp. 657-660
Type of Manuscript:  LETTER
Category: Neural Networks
Keyword: 
circuit simulationgate level partitioningwaveform relaxationtransmission lines
 Summary | Full Text:PDF(235.4KB)

Relaxation-Based Circuit Simulation Techniques in the Frequency Domain
Hiroaki MAKINO Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/04/25
Vol. E76-A  No. 4  pp. 626-630
Type of Manuscript:  PAPER
Category: Modeling and Simulation
Keyword: 
harmonic balancerelaxationcircuit simulationlatencyfrequency domain
 Summary | Full Text:PDF(388.8KB)

Mixed Mode Circuit Simulation Using Dynamic Partitioning
Masakatsu NISHIGAKI Nobuyuki TANAKA Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/03/25
Vol. E76-A  No. 3  pp. 292-298
Type of Manuscript:  Special Section PAPER (Special Section on the 5th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
circuit simulationmixed mode simulationdynamic partitioninghierarchical decompositionlatency
 Summary | Full Text:PDF(620.8KB)

Bipolar Transistor Circuit Analysis by Waveform Relaxation Method with Consideration of the Operation Point
Koichi HAYASHI Mitsuru KOMATSU Masakatsu NISHIGAKI Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/07/25
Vol. E75-A  No. 7  pp. 914-916
Type of Manuscript:  Special Section LETTER (Special Section on the 1992 IEICE Spring Conference)
Category: 
Keyword: 
circuit simulationwaveform relaxationdynamic partitioningbipolar transistor circuit
 Summary | Full Text:PDF(154.2KB)

Numerical Stability and Multirate Effect in Waveform Relaxation Algorithm with Under Relaxation Technique
Koichi HAYASHI Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/06/25
Vol. E75-A  No. 6  pp. 685-690
Type of Manuscript:  Special Section PAPER (Special Section of Papers Selected from 1991 Joint Technical Conference on Circuits/Systems, Computers and Communications (JTC-CSCC '91))
Category: Combinational/Numerical/Graphic Algorithms
Keyword: 
multirate behaviorwaveform relaxation algorithmunder relaxation techniquevirtual state formulationnumerical stability
 Summary | Full Text:PDF(396.3KB)

Hierarchical Decomposition and Latency for Circuit Simulation by Direct Method
Masakatsu NISHIGAKI Nobuyuki TANAKA Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/03/25
Vol. E75-A  No. 3  pp. 347-351
Type of Manuscript:  Special Section LETTER (Special Section on the 4th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
circuit simulation network tearinghierarchical decompositionlatency
 Summary | Full Text:PDF(262.3KB)

Iterated Spectrum Analysis with Multirate Behavior
Hiroaki MAKINO Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1991/05/25
Vol. E74-A  No. 5  pp. 1006-1008
Type of Manuscript:  Special Section LETTER (Special Issue on 1991 Spring Natl. Conv. IEICE)
Category: Nonlinear Problems and Simulation
Keyword: 
 Summary | Full Text:PDF(152.4KB)

Availability of Waveform Relaxation Method with Local Iteration and Window Partition Techniques
Kazuo ENDOH Nobuyuki TANAKA Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1991/05/25
Vol. E74-A  No. 5  pp. 1003-1005
Type of Manuscript:  Special Section LETTER (Special Issue on 1991 Spring Natl. Conv. IEICE)
Category: Nonlinear Problems and Simulation
Keyword: 
 Summary | Full Text:PDF(136.2KB)

Effect of Multirate Behavior in Waveform Relaxation Algorithm with Under Relaxation Technique
Koichi HAYASHI Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1991/05/25
Vol. E74-A  No. 5  pp. 1009-1010
Type of Manuscript:  Special Section LETTER (Special Issue on 1991 Spring Natl. Conv. IEICE)
Category: Nonlinear Problems and Simulation
Keyword: 
 Summary | Full Text:PDF(130.8KB)

Hierarchical Decomposition for Circuit Simulation by Direct Method
Masakatsu NISHIGAKI Nobuyuki TANAKA Hideki ASAI 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1990/12/25
Vol. E73-E  No. 12  pp. 1948-1956
Type of Manuscript:  Special Section PAPER (Special Issue on the 3rd Karuizawa Workshop on Circuits and Systems)
Category: Nonlinear Circuits and Simulation
Keyword: 
 Summary | Full Text:PDF(637.7KB)

Large Scale Circuit Simulation System with Dedicated Parallel Processor SMASH
Nobuyuki TANAKA Hideki ASAI 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1990/12/25
Vol. E73-E  No. 12  pp. 1957-1963
Type of Manuscript:  Special Section PAPER (Special Issue on the 3rd Karuizawa Workshop on Circuits and Systems)
Category: Nonlinear Circuits and Simulation
Keyword: 
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Special Parallel Machine for LU Decomposition of a Large Scale Circuit Matrix and Its Performance
Nobuyuki TANAKA Hideki ASAI 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1989/12/25
Vol. E72-E  No. 12  pp. 1336-1343
Type of Manuscript:  Special Section PAPER (Special Issue on the 2nd Karuizawa Workshop on Circuits and Systems)
Category: VLSI Design Technology
Keyword: 
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Analogy between Stabilization Techniques for Relaxation-Based Algorithms
Hideki ASAI 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1989/10/25
Vol. E72-E  No. 10  pp. 1079-1080
Type of Manuscript:  LETTER
Category: Numerical Calculation and Mathematical Programming
Keyword: 
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Availability of Gate Level Node Tearing in Bipolar Circuit Simulation by Direct Method
Hideki ASAI Atsushi KUMITA 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1988/10/25
Vol. E71-E  No. 10  pp. 962-964
Type of Manuscript:  LETTER
Category: Numerical Calculation and Mathematical Programming
Keyword: 
 Summary | Full Text:PDF(161.5KB)