Hideki ANDO


FXA: Executing Instructions in Front-End for Energy Efficiency
Ryota SHIOYA Ryo TAKAMI Masahiro GOSHIMA Hideki ANDO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/04/01
Vol. E99-D  No. 4  pp. 1092-1107
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
superscalar processorhybrid in-order/out-of-order coreenergy efficiency
 Summary | Full Text:PDF(1.3MB)

Improvement of Renamed Trace Cache through the Reduction of Dependent Path Length for High Energy Efficiency
Ryota SHIOYA Hideki ANDO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/03/01
Vol. E99-D  No. 3  pp. 630-640
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
superscalar processorregister renamingtrace cacheenergy efficiency
 Summary | Full Text:PDF(1MB)

Performance of Dynamic Instruction Window Resizing for a Given Power Budget under DVFS Control
Hideki ANDO Ryota SHIOYA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/02/01
Vol. E99-D  No. 2  pp. 341-350
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
microprocessorsuperscalar processormemory-level parallelisminstruction-level parallelismpower consumption
 Summary | Full Text:PDF(638.6KB)

MLP-Aware Dynamic Instruction Window Resizing in Superscalar Processors for Adaptively Exploiting Available Parallelism
Yuya KORA Kyohei YAMAGUCHI Hideki ANDO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/12/01
Vol. E97-D  No. 12  pp. 3110-3123
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
microprocessorsuperscalar processormemory-level parallelisminstruction-level parallelism
 Summary | Full Text:PDF(1.6MB)

Delay Evaluation of Issue Queue in Superscalar Processors with Banking Tag RAM and Correct Critical Path Identification
Kyohei YAMAGUCHI Yuya KORA Hideki ANDO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/09/01
Vol. E95-D  No. 9  pp. 2235-2246
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
microprocessorsuperscalar processorissue queuedelaycomplexity
 Summary | Full Text:PDF(874.5KB)

Register File Size Reduction through Instruction Pre-Execution Incorporating Value Prediction
Yusuke TANAKA Hideki ANDO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/12/01
Vol. E93-D  No. 12  pp. 3294-3305
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
microarchitecturemicroprocessorinstruction pre-executionvalue predictionregister file
 Summary | Full Text:PDF(541.3KB)

Energy-Efficient Pre-Execution Techniques in Two-Step Physical Register Deallocation
Kazunaga HYODO Kengo IWAMOTO Hideki ANDO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2009/11/01
Vol. E92-D  No. 11  pp. 2186-2195
Type of Manuscript:  PAPER
Category: Computer Systems
Keyword: 
microarchitecturemicroprocessorinstruction pre-executionlow power
 Summary | Full Text:PDF(520.3KB)

Speculative Execution and Reducing Branch Penalty on a Superscalar Processor
Hideki ANDO Chikako NAKANISHI Hirohisa MACHIDA Tetsuya HARA Masao NAKAYA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/07/25
Vol. E76-C  No. 7  pp. 1080-1093
Type of Manuscript:  Special Section PAPER (Special Issue on New Architecture LSIs)
Category: Improved Binary Digital Architectures
Keyword: 
superscalarVLIWspeculative execution
 Summary | Full Text:PDF(1.2MB)