IEICE SEARCH SYSTEM

Hideharu AMANO

Leakage Power Reduction of a Dynamically Reconfigurable Processor Using Dual-Vth Cells Keiichiro HIRAI Toru SANO Masaru KATO Yoshiki SAITO Hideharu AMANO
Publication: D - Abstracts of IEICE TRANSACTIONS on Information and Systems (Japanese Edition) Publication Date: 2011/01/01 Vol. J94-D No. 1 pp. 303-311 Type of Manuscript: PAPER Category: Keyword: dynamically reconfigurable processor, low leakage design, Dual-Vth,
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Data Bus Configuration: Configuration Data Transfer Time Reduction Method for Dynamically Reconfigurable Devices Toru SANO Masaru KATO Yoshiki SAITO Hideharu AMANO
Publication: D - Abstracts of IEICE TRANSACTIONS on Information and Systems (Japanese Edition) Publication Date: 2010/12/01 Vol. J93-D No. 12 pp. 2579-2586 Type of Manuscript: PAPER Category: Keyword: dynamically reconfigurable processor array, configuration data transfer time,
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A Fine Grain Dynamic Sleep Control Scheme in MIPS R3000 Naomi SEKI Lei ZHAO Yu KOJIMA Daisuke IKEBUCHI Yohei HASEGAWA Naoaki OHKUBO Seidai TAKEDA Toshihiro KASHIMA Toshiaki SHIRAI Kimiyoshi USAMI Tetsuya SUNATA Jun KANAI Mitaro NAMIKI Hiroaki KONDO Hiroshi NAKAMURA Hideharu AMANO
Publication: D - Abstracts of IEICE TRANSACTIONS on Information and Systems (Japanese Edition) Publication Date: 2010/06/01 Vol. J93-D No. 6 pp. 920-930 Type of Manuscript: PAPER Category: Keyword: low power processor, power gating, leakage,
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Multi-Cast Methods for Configuration Data Transfer on Dynamically Reconfigurable Devices Takuro NAKAMURA Toru SANO Satoshi TSUTSUMI Yohei HASEGAWA Vasutan TUNBUNHENG Hideharu AMANO
Publication: D - Abstracts of IEICE TRANSACTIONS on Information and Systems (Japanese Edition) Publication Date: 2009/12/01 Vol. J92-D No. 12 pp. 2185-2194 Type of Manuscript: PAPER Category: Keyword: dynamically reconfigurable processor, configuration scheme,
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Power Analysis and Power Reduction Techniques for Dynamically Reconfigurable Processors Takashi NISHIMURA Keiichiro HIRAI Yoshiki SAITO Takuro NAKAMURA Satoshi TSUTSUMI Yohei HASEGAWA Hideharu AMANO
Publication: D - Abstracts of IEICE TRANSACTIONS on Information and Systems (Japanese Edition) Publication Date: 2009/10/01 Vol. J92-D No. 10 pp. 1763-1771 Type of Manuscript: PAPER Category: Keyword: dynamically reconfigurable processor, low power consumption,
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Cost Effective Dynamic Binary Translation for Performance Simulator ESPRIT/sim Yasuhito OHMIYA Hideharu AMANO
Publication: D - Abstracts of IEICE TRANSACTIONS on Information and Systems (Japanese Edition) Publication Date: 2008/10/01 Vol. J91-D No. 10 pp. 2449-2465 Type of Manuscript: PAPER Category: Keyword: binary translation, instruction simulator, instruction emulator, instruction interpreter, architectural emulation, processor simulation,
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A Biochemical Model Compiler for Simulations on an FPGA Yow IWAOKA Yasunori OSANA Masato YOSHIMI Yuri NISHIKAWA Toshinori KOJIMA Akira FUNAHASHI Noriko HIROI Yuichiro SHIBATA Naoki IWANAGA Hiroaki KITANO Hideharu AMANO
Publication: D - Abstracts of IEICE TRANSACTIONS on Information and Systems (Japanese Edition) Publication Date: 2008/09/01 Vol. J91-D No. 9 pp. 2205-2216 Type of Manuscript: PAPER Category: Keyword: FPGA, biochemical simulations, SBML,
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An Overwrite Configuration Technique for Multicast Configuration Scheme Satoshi TSUTSUMI Vasutan TUNBUNHENG Yohei HASEGAWA Adepu PARIMALA Takuro NAKAMURA Takashi NISHIMURA Hideharu AMANO
Publication: D - Abstracts of IEICE TRANSACTIONS on Information and Systems (Japanese Edition) Publication Date: 2008/04/01 Vol. J91-D No. 4 pp. 922-933 Type of Manuscript: PAPER Category: Keyword: dynamically reconfigurable processor, configuration scheme, scheduling,
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Performance Improvement of Interpreter-type Emulator Written in C-Language Yasuhito OHMIYA Hideharu AMANO
Publication: D - Abstracts of IEICE TRANSACTIONS on Information and Systems (Japanese Edition) Publication Date: 2008/02/01 Vol. J91-D No. 2 pp. 413-434 Type of Manuscript: PAPER Category: Keyword: instruction simulator, instruction emulator, instruction interpreter, architectural emulation, processor simulation,
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A Reconfigurable System for Identification of Cell Division Patterns in Early Embryogenesis of Caenorhabdits elegans Tomonori FUKUSIMA Yasunori OSANA Tomonori TAMURA Shugo HAMAHASHI Shuichi ONAMI Hideharu AMANO
Publication: D - Abstracts of IEICE TRANSACTIONS on Information and Systems (Japanese Edition) Publication Date: 2007/11/01 Vol. J90-D No. 11 pp. 2970-2980 Type of Manuscript: PAPER Category: Keyword: reconfigurable system, bioinformatics, image processing,
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A Clock Control Mechanism Using Context Dependent Delay for Dynamically Reconfigurable Processors Satoshi TSUTSUMI Hideharu AMANO Yohei HASEGAWA Ken'ichiro ISHIKAWA Shohei ABE Shunsuke KUROTAKI Takuro NAKAMURA Takashi NISHIMURA
Publication: D - Abstracts of IEICE TRANSACTIONS on Information and Systems (Japanese Edition) Publication Date: 2007/10/01 Vol. J90-D No. 10 pp. 2704-2712 Type of Manuscript: PAPER Category: Keyword: dynamically reconfigurable processor, context control, clock control,
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Implementation and Evaluation of RHiNET-2 System: The Parallel and Distributed Processing Environment Konosuke WATANABE Tomohiro OTSUKA Hideharu AMANO
Publication: D - Abstracts of IEICE TRANSACTIONS on Information and Systems (Japanese Edition) Publication Date: 2007/09/01 Vol. J90-D No. 9 pp. 2465-2482 Type of Manuscript: PAPER Category: Keyword: PC clusters, high-performance network, parallel processing, system software, performance evaluation, SCore,
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Implementation of a Super-Scalar Processor Model for Multiprocessor System Simulator Development Yasuki TANABE Toshihiro HANAWA Hideharu AMANO
Publication: D - Abstracts of IEICE TRANSACTIONS on Information and Systems (Japanese Edition) Publication Date: 2007/06/01 Vol. J90-D No. 6 pp. 1428-1444 Type of Manuscript: PAPER Category: Keyword: multiprocessor system, performance evaluation, simulator, development support, super-scalar processor,
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Implementation and Evaluation of Sound Source Separation Filter on Dynamically Reconfigurable Processor Shunsuke KUROTAKI Noriaki SUZUKI Kazuhiro NAKADAI Hiroshi G. OKUNO Hideharu AMANO
Publication: D - Abstracts of IEICE TRANSACTIONS on Information and Systems (Japanese Edition) Publication Date: 2007/03/01 Vol. J90-D No. 3 pp. 897-907 Type of Manuscript: PAPER Category: Keyword: dynamically reconfigurable device, DRP, robot audition, sound source separation,
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Proposal and Evaluation of Synchronous Speculative Completion Ken-ichiro ISHIKAWA Yoshinori ADACHI Hideharu AMANO
Publication: D - Abstracts of IEICE TRANSACTIONS on Information and Systems (Japanese Edition) Publication Date: 2006/11/01 Vol. J89-D No. 11 pp. 2396-2403 Type of Manuscript: PAPER Category: Keyword: speculative completion, CPU core, performance evaluation,
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Fat H-Tree: An Interconnection Network for Reconfigurable Processor Array Yutaka YAMADA Hideharu AMANO Michihiro KOIBUCHI Akiya JOURAKU Kenichiro ANJO
Publication: D - Abstracts of IEICE TRANSACTIONS on Information and Systems (Japanese Edition) Publication Date: 2006/09/01 Vol. J89-D No. 9 pp. 1923-1934 Type of Manuscript: PAPER Category: Keyword: network-on-a-chip, topology, reconfigurable processor, fat H-tree,
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Arixar--The Asynchronous Multicontext Device Yoshinori ADACHI Satoshi TSUTSUMI Hideharu AMANO
Publication: D - Abstracts of IEICE TRANSACTIONS on Information and Systems (Japanese Edition) Publication Date: 2006/08/01 Vol. J89-D No. 8 pp. 1739-1750 Type of Manuscript: PAPER Category: Keyword: asynchronous circuit, multicontext device, AES,
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A Novel Cost-Effective Context Memory Structure for Dynamically Reconfigurable Processors Masayasu SUZUKI Yohei HASEGAWA Shohei ABE Vu Manh TUAN Hideharu AMANO
Publication: D - Abstracts of IEICE TRANSACTIONS on Information and Systems (Japanese Edition) Publication Date: 2006/06/01 Vol. J89-D No. 6 pp. 1101-1109 Type of Manuscript: Special Section PAPER (Special Issue Reconfigurable Systems) Category: Keyword: dynamically reconfigurable processor, multi-context scheme, high speed configuration,
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ReCSiP: An FPGA-Based General Purpose Biochemical Simulator Yasunori OSANE Masato YOSHIMI Yow IWAOKA Toshinori KOJIMA Yuri NISHIKAWA Akira FUNAHASHI Noriko HIROI Yuichiro SHIBATA Naoki IWANAGA Hiroaki KITANO Hideharu AMANO
Publication: D - Abstracts of IEICE TRANSACTIONS on Information and Systems (Japanese Edition) Publication Date: 2006/06/01 Vol. J89-D No. 6 pp. 1163-1172 Type of Manuscript: Special Section PAPER (Special Issue Reconfigurable Systems) Category: Keyword: FPGA, biochemical simulations, ordinary differential equations, rate-law functions, Runge-Kutta method,
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An Adaptive Cryptographic Accelerator for IPsec on the Dynamically Reconfigurable Processor Yohei HASEGAWA Shohei ABE Hiroki MATSUTANI Kenichiro ANJO Toru AWASHIMA Hideharu AMANO
Publication: D - Abstracts of IEICE TRANSACTIONS on Information and Systems (Japanese Edition) Publication Date: 2006/04/01 Vol. J89-D No. 4 pp. 743-754 Type of Manuscript: PAPER Category: Keyword: dynamically reconfigurable processor, DRP, virtual hardware, IP security,
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