Hideharu AMANO


Novel Chip Stacking Methods to Extend Both Horizontally and Vertically for Many-Core Architectures with ThrouChip Interface
Hiroshi NAKAHARA Tomoya OZAKI Hiroki MATSUTANI Michihiro KOIBUCHI Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/12/01
Vol. E99-D  No. 12  pp. 2871-2880
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: Architecture
Keyword: 
inductive coupling interconnectinterconnection networknetwork on chip
 Summary | Full Text:PDF(1.7MB)

An Operating System Guided Fine-Grained Power Gating Control Based on Runtime Characteristics of Applications
Atsushi KOSHIBA Mikiko SATO Kimiyoshi USAMI Hideharu AMANO Ryuichi SAKAMOTO Masaaki KONDO Hiroshi NAKAMURA Mitaro NAMIKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2016/08/01
Vol. E99-C  No. 8  pp. 926-935
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power and High-Speed Chips)
Category: 
Keyword: 
energy conservationpower gatingoperating systemmicroprocessor
 Summary | Full Text:PDF(2.7MB)

Multi-Voltage Variable Pipeline Routers with the Same Clock Frequency for Low-Power Network-on-Chips Systems
Akram BEN AHMED Hiroki MATSUTANI Michihiro KOIBUCHI Kimiyoshi USAMI Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2016/08/01
Vol. E99-C  No. 8  pp. 909-917
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power and High-Speed Chips)
Category: 
Keyword: 
Network-on-Chipsmulti-Vddlow power networks
 Summary | Full Text:PDF(797.3KB)

A Perpetuum Mobile 32bit CPU on 65nm SOTB CMOS Technology with Reverse-Body-Bias Assisted Sleep Mode
Koichiro ISHIBASHI Nobuyuki SUGII Shiro KAMOHARA Kimiyoshi USAMI Hideharu AMANO Kazutoshi KOBAYASHI Cong-Kha PHAM 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2015/07/01
Vol. E98-C  No. 7  pp. 536-543
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power and High-Speed Chips)
Category: 
Keyword: 
microprocessorlow power design
 Summary | Full Text:PDF(2.2MB)

A Fine-Grained Power Gating Control on Linux Monitoring Power Consumption of Processor Functional Units
Atsushi KOSHIBA Motoki WADA Ryuichi SAKAMOTO Mikiko SATO Tsubasa KOSAKA Kimiyoshi USAMI Hideharu AMANO Masaaki KONDO Hiroshi NAKAMURA Mitaro NAMIKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2015/07/01
Vol. E98-C  No. 7  pp. 559-568
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power and High-Speed Chips)
Category: 
Keyword: 
energy conservationpower gatingoperating systemLinux
 Summary | Full Text:PDF(2.1MB)

Reconfigurable Out-of-Order System for Fluid Dynamics Computation Using Unstructured Mesh
Takayuki AKAMINE Mohamad Sofian ABU TALIP Yasunori OSANA Naoyuki FUJITA Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/05/01
Vol. E97-D  No. 5  pp. 1225-1234
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
computational fluid dynamics (CFD)field programmable gate array (FPGA)scientific computationsreconfigurable hardwareout-of-order system
 Summary | Full Text:PDF(1MB)

Vertical Link On/Off Regulations for Inductive-Coupling Based Wireless 3-D NoCs
Hao ZHANG Hiroki MATSUTANI Yasuhiro TAKE Tadahiro KURODA Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/12/01
Vol. E96-D  No. 12  pp. 2753-2764
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
3-D network on chip (3-D NoC)wirelessinductive-couplinglow poweron/off vertical link
 Summary | Full Text:PDF(2MB)

FOREWORD
Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/08/01
Vol. E96-D  No. 8  pp. 1581-1581
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF(81.9KB)

High-Speed Fully-Adaptable CRC Accelerators
Amila AKAGIC Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/06/01
Vol. E96-D  No. 6  pp. 1299-1308
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
reconfigurable computingFPGAscyclic redundancy checksadaptabilityaccelerators
 Summary | Full Text:PDF(1.2MB)

Fine-Grained Run-Tume Power Gating through Co-optimization of Circuit, Architecture, and System Software Design
Hiroshi NAKAMURA Weihan WANG Yuya OHTA Kimiyoshi USAMI Hideharu AMANO Masaaki KONDO Mitaro NAMIKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/04/01
Vol. E96-C  No. 4  pp. 404-412
Type of Manuscript:  INVITED PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
low-power circuit techniquesfine grained power-gatingcompilersystem hierarchy cooperation
 Summary | Full Text:PDF(3.1MB)

FOREWORD
Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/12/01
Vol. E95-D  No. 12  pp. 2749-2749
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF(70.2KB)

Partial Reconfiguration of Flux Limiter Functions in MUSCL Scheme Using FPGA
Mohamad Sofian ABU TALIP Takayuki AKAMINE Yasunori OSANA Naoyuki FUJITA Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/10/01
Vol. E95-D  No. 10  pp. 2369-2376
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
computational fluid dynamics (CFD)field programmable gate array (FPGA)scientific computationsreconfigurable hardwarepartial reconfiguration
 Summary | Full Text:PDF(676.8KB)

FOREWORD
Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/02/01
Vol. E95-D  No. 2  pp. 293-293
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF(52.6KB)

Iterative Synthesis Methods Estimating Programmable-Wire Congestion in a Dynamically Reconfigurable Processor
Takao TOI Takumi OKAMOTO Toru AWASHIMA Kazutoshi WAKABAYASHI Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12  pp. 2619-2627
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
coarse-grained reconfigurable architecturedynamically reconfigurable processorhigh-level synthesisiterative synthesiswire delay
 Summary | Full Text:PDF(2.1MB)

A Leakage Efficient Instruction TLB Design for Embedded Processors
Zhao LEI Hui XU Daisuke IKEBUCHI Tetsuya SUNATA Mitaro NAMIKI Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/08/01
Vol. E94-D  No. 8  pp. 1565-1574
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
leakage powerTLBembedded processor
 Summary | Full Text:PDF(1.3MB)

A Leakage Efficient Data TLB Design for Embedded Processors
Zhao LEI Hui XU Daisuke IKEBUCHI Tetsuya SUNATA Mitaro NAMIKI Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/01/01
Vol. E94-D  No. 1  pp. 51-59
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
leakage powerTLBembedded processor
 Summary | Full Text:PDF(921.7KB)

Code Compression with Split Echo Instructions
Iver STUBDAL Arda KARADUMAN Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2009/09/01
Vol. E92-D  No. 9  pp. 1650-1656
Type of Manuscript:  PAPER
Category: Fundamentals of Software and Theory of Programs
Keyword: 
code sizeecho instructionscompressionMIPS processor
 Summary | Full Text:PDF(449.9KB)

A Link Removal Methodology for Application-Specific Networks-on-Chip on FPGAs
Daihan WANG Hiroki MATSUTANI Michihiro KOIBUCHI Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2009/04/01
Vol. E92-D  No. 4  pp. 575-583
Type of Manuscript:  PAPER
Category: VLSI Systems
Keyword: 
network-on-chipFPGAcustomizerouter
 Summary | Full Text:PDF(491KB)

A Preemption Algorithm for a Multitasking Environment on Dynamically Reconfigurable Processors
Vu Manh TUAN Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/12/01
Vol. E91-D  No. 12  pp. 2793-2803
Type of Manuscript:  PAPER
Category: Computer Systems
Keyword: 
dynamically reconfigurable processorpreemption algorithmpreemption latencyhardware overhead
 Summary | Full Text:PDF(350.9KB)

A Retargetable Compiler Based on Graph Representation for Dynamically Reconfigurable Processor Arrays
Vasutan TUNBUNHENG Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/11/01
Vol. E91-D  No. 11  pp. 2655-2665
Type of Manuscript:  PAPER
Category: VLSI Systems
Keyword: 
dynamically reconfigurable systemretargetable compiler
 Summary | Full Text:PDF(918.1KB)

A Mapping Method for Multi-Process Execution on Dynamically Reconfigurable Processors
Vu MANH TUAN Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/09/01
Vol. E91-D  No. 9  pp. 2312-2322
Type of Manuscript:  PAPER
Category: Computer Systems
Keyword: 
dynamically reconfigurable processormulti-process executionsingle-process execution
 Summary | Full Text:PDF(380.7KB)

A Port Combination Methodology for Application-Specific Networks-on-Chip on FPGAs
Daihan WANG Hiroki MATSUTANI Michihiro KOIBUCHI Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/12/01
Vol. E90-D  No. 12  pp. 1914-1922
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Reconfigurable System and Applications
Keyword: 
Networks-on-ChipFPGArouterport combination
 Summary | Full Text:PDF(467.3KB)

Data Multicasting Procedure for Increasing Configuration Speed of Coarse Grain Reconfigurable Devices
Vasutan TUNBUNHENG Masayasu SUZUKI Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/02/01
Vol. E90-D  No. 2  pp. 473-481
Type of Manuscript:  PAPER
Category: Computer Systems
Keyword: 
dynamically reconfigurable systemhigh speed configurationconfiguration network
 Summary | Full Text:PDF(913.7KB)

A Survey on Dynamically Reconfigurable Processors
Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2006/12/01
Vol. E89-B  No. 12  pp. 3179-3187
Type of Manuscript:  INVITED PAPER (Special Section on Software Defined Radio Technology and Its Applications)
Category: 
Keyword: 
dynamically reconfigurable processors
 Summary | Full Text:PDF(754.1KB)

MMLRU Selection Function: A Simple and Efficient Output Selection Function in Adaptive Routing
Michihiro KOIBUCHI Akiya JOURAKU Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/01/01
Vol. E88-D  No. 1  pp. 109-118
Type of Manuscript:  PAPER
Category: Computer Systems
Keyword: 
output selection functionadaptive routingvirtual channelinterconnection networksmassively parallel computers
 Summary | Full Text:PDF(525KB)

An FPGA-Based Acceleration Method for Metabolic Simulation
Yasunori OSANA Tomonori FUKUSHIMA Masato YOSHIMI Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/08/01
Vol. E87-D  No. 8  pp. 2029-2037
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Recornfigurable Systems
Keyword: 
metabolic simulationordinary differential equationsFPGA
 Summary | Full Text:PDF(546.4KB)

A Dynamically Adaptive Hardware on Dynamically Reconfigurable Processor
Hideharu AMANO Akiya JOURAKU Kenichiro ANJO 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2003/12/01
Vol. E86-B  No. 12  pp. 3385-3391
Type of Manuscript:  INVITED PAPER (Special Issue on Software Defined Radio Technology and Its Applications)
Category: 
Keyword: 
dynamically reconfigurable systemsinterconnection network
 Summary | Full Text:PDF(479.1KB)

Performance Evaluation of Instruction Set Architecture of MBP-Light in JUMP-1
Noriaki SUZUKI Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/10/01
Vol. E86-D  No. 10  pp. 1996-2005
Type of Manuscript:  Special Section PAPER (Special Issue on Development of Advanced Computer Systems)
Category: 
Keyword: 
CC-NUMADSM managementinstruction set architecture
 Summary | Full Text:PDF(432.8KB)

Pot: A General Purpose Monitor for Parallel Computers
Yuso KANAMORI Oki MINABE Masaki WAKABAYASHI Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/10/01
Vol. E86-D  No. 10  pp. 2025-2033
Type of Manuscript:  Special Section PAPER (Special Issue on Development of Advanced Computer Systems)
Category: 
Keyword: 
parallel architecturessoftware development environmentmonitoring system
 Summary | Full Text:PDF(670.1KB)

Architecture and Evaluation of a Third-Generation RHiNET Switch for High-Performance Parallel Computing
Hiroaki NISHI Shinji NISHIMURA Katsuyoshi HARASAWA Tomohiro KUDOH Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/10/01
Vol. E86-D  No. 10  pp. 1987-1995
Type of Manuscript:  Special Section PAPER (Special Issue on Development of Advanced Computer Systems)
Category: 
Keyword: 
RHiNETcluster computing networkhigh-performance systemflow control
 Summary | Full Text:PDF(762.7KB)

Implementation of Data Driven Applications on a Multi-Context Reconfigurable Device
Masaki UNO Yuichiro SHIBATA Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/05/01
Vol. E86-D  No. 5  pp. 841-849
Type of Manuscript:  Special Section PAPER (Special Issue on Reconfigurable Computing)
Category: 
Keyword: 
reconfigurable machinesdata driven control
 Summary | Full Text:PDF(283KB)

Design and Implementation of RHiNET-2/NI0: A Reconfigurable Network Interface for Cluster Computing
Tomonori YOKOYAMA Naoyuki IZU Jun-ichiro TSUCHIYA Konosuke WATANABE Hideharu AMANO Tomohiro KUDOH 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/05/01
Vol. E86-D  No. 5  pp. 789-795
Type of Manuscript:  Special Section PAPER (Special Issue on Reconfigurable Computing)
Category: 
Keyword: 
reconfigurable machinesnetwork interfacesystem area network
 Summary | Full Text:PDF(765.6KB)

A Routing Algorithm for Multihop WDM Ring
Xiaoshe DONG Tomohiro KUDOH Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/02/25
Vol. E82-D  No. 2  pp. 422-430
Type of Manuscript:  PAPER
Category: Computer Networks
Keyword: 
interconnection networkoptical communicationwavelength division multiplexing (WDM)parallel machinerouting algorithm
 Summary | Full Text:PDF(228.3KB)

Wavelength Division Multiple Access Ring -- Virtual Topology on a Simple Ring Network --
Xiaoshe DONG Tomohiro KUDOH Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/04/25
Vol. E81-D  No. 4  pp. 345-354
Type of Manuscript:  PAPER
Category: Computer Systems
Keyword: 
interconnection networkoptical communicationwavelength division multiple access (WDMA)parallel machinerouting algorithm
 Summary | Full Text:PDF(779.6KB)

MINC: Multistage Interconnection Network with Cache Control Mechanism
Toshihiro HANAWA Takayuki KAMEI Hideki YASUKAWA Katsunobu NISHIMURA Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/09/25
Vol. E80-D  No. 9  pp. 863-870
Type of Manuscript:  Special Section PAPER (Special Issue on Architectures, Algorithms and Networks for Massively Parallel Computing)
Category: Interconnection Networks
Keyword: 
MINcoherent cachedirectory schememultiprocessorcongestion analysisVLSI implementation
 Summary | Full Text:PDF(721.1KB)

The RDT Router Chip: A Versatile Router for Supporting a Distributed Shared Memory
Hiroaki NISHI Ken-ichiro ANJO Tomohiro KUDOH Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/09/25
Vol. E80-D  No. 9  pp. 854-862
Type of Manuscript:  Special Section PAPER (Special Issue on Architectures, Algorithms and Networks for Massively Parallel Computing)
Category: Interconnection Networks
Keyword: 
routerinterconnection networkcache coherent distributed shared memory
 Summary | Full Text:PDF(794.5KB)

Fault Tolerance of the TBSF (Tandem Banyan Switching Fabrics) and PBSF (Piled Banyan Switching Fabrics)
Akira FUNAHASHI Toshihiro HANAWA Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/08/25
Vol. E79-D  No. 8  pp. 1180-1189
Type of Manuscript:  Special Section PAPER (Special Issue on Architectures, Algorithms and Networks for Massively Parallel Computing)
Category: Fault Diagnosis/Tolerance
Keyword: 
Multistage Interconnection Network (MIN)MIN with multiple outletsfault tolerance
 Summary | Full Text:PDF(767.7KB)

The MDX (Multi-Dimensional X'bar): A Class of Networks for Large Scale Multiprocessors
Atsushi MURATA Taisuke BOKU Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/08/25
Vol. E79-D  No. 8  pp. 1116-1123
Type of Manuscript:  Special Section PAPER (Special Issue on Architectures, Algorithms and Networks for Massively Parallel Computing)
Category: Interconnection Networks
Keyword: 
interconnection networkcrossbarMINmultiprocessors
 Summary | Full Text:PDF(605.2KB)

Message Transfer Algorithms on the Recursive Diagonal Torus
Yulu YANG Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/02/25
Vol. E79-D  No. 2  pp. 107-116
Type of Manuscript:  PAPER
Category: Computer Systems
Keyword: 
interconnection networkrouting algorithmbroadcastdeadlock-free
 Summary | Full Text:PDF(844.4KB)

A Batcher-Double-Omega Network with Combining
Kalidou GAYE Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1992/05/25
Vol. E75-D  No. 3  pp. 307-314
Type of Manuscript:  PAPER
Category: Computer Networks
Keyword: 
Interconnection networksmultiprocessorsmessage combining
 Summary | Full Text:PDF(586.7KB)

The Compatible Acknowledging Ethernet
Toshitada SAITO Mario TOKORO Hideharu AMANO 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1987/10/25
Vol. E70-E  No. 10  pp. 960-967
Type of Manuscript:  PAPER
Category: Switching and Communication Processing
Keyword: 
 Summary | Full Text:PDF(533.6KB)

A VLSI Switch for a Digital PBX
Suhut Hasiholan PURBA Hideharu AMANO Yasuro SHOBATAKE Hideo AISO 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1986/07/25
Vol. E69-E  No. 7  pp. 771-774
Type of Manuscript:  LETTER
Category: Switching Systems and Communication Processing
Keyword: 
 Summary | Full Text:PDF(229.1KB)