Hajime NOBUSAWA


Design of 1024-I/Os 3. 84 GB/s High Bandwidth 600 mW Low Power 16 Mb DRAM Macros for Parallel Image Processing RAM
Yoshiharu AIMOTO  Tohru KIMURA  Yoshikazu YABE  Hideki HEIUCHI  Youetsu NAKAZAWA  Masato MOTOMURA  Takuya KOGA  Yoshihiro FUJITA  Masayuki HAMADA  Takaho TANIGAWA  Hajime NOBUSAWA  Kuniaki KOYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/05/20
Vol. E81-C  No. 5  pp. 759-767
Type of Manuscript: Special Section PAPER (Special Issue on Multimedia, Network, and DRAM LSIs)
Category: 
Keyword: 
integration of DRAM and logicembedded DRAMlow powerhigh memory bandwidth
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