Hachiro YAMADA


Analysis of the Effects of Offset Errors in Neural LSIs
Fuyuki OKAMOTO Hachiro YAMADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/09/25
Vol. E80-A  No. 9  pp. 1640-1646
Type of Manuscript:  PAPER
Category: Analog Signal Processing
Keyword: 
neural networkanalog LSIoffset errorstochastic gradient descent ruleperceptron
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Cache-Processor Coupling: A Fast and Wide On-Chip Data Cache Design
Masato MOTOMURA Toshiaki INOUE Hachiro YAMADA Akihiko KONAGAYA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/06/25
Vol. E78-C  No. 6  pp. 623-630
Type of Manuscript:  Special Section PAPER (Special Issue on the 1994 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol. 30, No. 4 April 1995))
Category: 
Keyword: 
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A PLL-Based Programmable Clock Generator with 50-to 350-MHz Oscillating Range for Video Signal Processors
Junichi GOTO Masakazu YAMASHINA Toshiaki INOUE Benjamin S. SHIH Youichi KOSEKI Tadahiko HORIUCHI Nobuhisa HAMATAKE Kouichi KUMAGAI Tadayoshi ENOMOTO Hachiro YAMADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/12/25
Vol. E77-C  No. 12  pp. 1951-1956
Type of Manuscript:  Special Section PAPER (Special Issue on Multimedia, Analog and Processing LSIs)
Category: Processor Interfaces
Keyword: 
electronic circuitsclock generatorPLLfrequency multiplicationVCOVCO gainjitterpull-in rangeCMOSVSP
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An MOS Current Mode Logic (MCML) Circuit for Low-Power Sub-GHz Processors
Masakazu YAMASHINA Hachiro YAMADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1992/10/25
Vol. E75-C  No. 10  pp. 1181-1187
Type of Manuscript:  Special Section PAPER (Special Issue on Microprocessors)
Category: Low-Voltage Operation
Keyword: 
current mode logiclow powerhigh speedMOS
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