Farhad MEHDIPOUR

Rapid Design Space Exploration of a Reconfigurable Instruction-Set Processor
Farhad MEHDIPOUR  Hamid NOORI  Koji INOUE  Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12  pp. 3182-3192
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Embedded, Real-Time and Reconfigurable Systems
Keyword: 
reconfigurable instruction-set processor,  analytical modeling,  design space exploration,  data flow graph accelerator, 
  Summary |  Full Text:PDF (1005.6KB)
A Reconfigurable Functional Unit with Conditional Execution for Multi-Exit Custom Instructions
Hamid NOORI  Farhad MEHDIPOUR  Koji INOUE  Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/04/01
Vol. E91-C  No. 4  pp. 497-508
Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories)
Category: 
Keyword: 
custom instructions,  extensible processor,  reconfigurable functional unit,  conditional execution, 
  Summary |  Full Text:PDF (1.5MB)
Improving Performance and Energy Saving in a Reconfigurable Processor via Accelerating Control Data Flow Graphs
Farhad MEHDIPOUR  Hamid NOORI  Morteza SAHEB ZAMANI  Koji INOUE  Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/12/01
Vol. E90-D  No. 12  pp. 1956-1966
Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Reconfigurable Device and Design Tools
Keyword: 
reconfigurable accelerator,  conditional execution,  control data flow graph,  temporal partitioning,  reconfigurable processor, 
  Summary |  Full Text:PDF (1.5MB)