Farhad Fuad ISLAM

Design of a Multiplier-Accumulator for High Speed lmage Filtering
Farhad Fuad ISLAM  Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/11/20
Vol. E76-A  No. 11  pp. 2022-2032
Type of Manuscript: PAPER
Category: VLSI Design Technology
Keyword: 
binary multiplier-accumulator,  throughput,  image filtering,  VLSI architecture, 
  Summary |  Full Text:PDF (845.1KB)
An Architecture for High Speed Array Multiplier
Farhad Fuad ISLAM  Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/08/20
Vol. E76-A  No. 8  pp. 1326-1333
Type of Manuscript: PAPER
Category: Computer Aided Design (CAD)
Keyword: 
binary multiplication,  array multipler,  VLSI architecture, 
  Summary |  Full Text:PDF (658.2KB)
An Architecture for FFT Butterfly Computation with Merged Core Multiplication technique
Farhad Fuad ISLAM  Hiroto YASUURA  Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1990/11/20
Vol. E73-E  No. 11  pp. 1810-1812
Type of Manuscript: Special Section LETTER (Special Issue on 1990 Autumn Natl. Conv. IEICE)
Category: Signals, Circuits and Images
Keyword: 
  Summary |  Full Text:PDF (180.5KB)