Eric MERCER


Partial Order Reduction for Timed Circuit Verification Based on Level Oriented Model
Tomoya KITAI Yusuke OGURO Tomohiro YONEDA Eric MERCER Chris MYERS 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/12/01
Vol. E86-D  No. 12  pp. 2601-2611
Type of Manuscript:  Special Section PAPER (Special Issue on Dependable Computing)
Category: Verification and Dependability Analysis
Keyword: 
Level-oriented modeltimed asynchronous circuitsformal verificationtime Petri nets
 Summary | Full Text:PDF(1006.1KB)

Modular Synthesis of Timed Circuits Using Partial Order Reduction
Tomohiro YONEDA Eric MERCER Chris MYERS 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A  No. 12  pp. 2684-2692
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
logic synthesispartial order reductiontimed circuitsmodular synthesis
 Summary | Full Text:PDF(568.5KB)