Edwin NAROSKA


Circuit Partition and Reordering Technique for Low Power IP Design
Kun-Lin TSAI Shanq-Jang RUAN Chun-Ming HUANG Edwin NAROSKA Feipei LAI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/04/01
Vol. E87-C  No. 4  pp. 613-620
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)
Category: 
Keyword: 
low powerstate reorderingcircuit partitionentropy
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