Dasisuke KATO


A 286 mm2 256 Mb DRAM with 32 Both-Ends DQ
Yohji WATANABE  Hing WONG  Toshiaki KIRIHATA  Dasisuke KATO  John K. DEBROSSE  Takahiko HARA  Munehiro YOSHIDA  Hideo MUKAI  Khandker N. QUADER  Takeshi NAGAI  Peter POECHMUELLER  Peter PFEFFERL  Matthew R. WORDEMAN  Shuso FUJII 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/07/20
Vol. E79-C  No. 7  pp. 978-985
Type of Manuscript: Special Section PAPER (Special Issue on the 1995 Symposium on VLSI Circuits (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.31, No.4 April 1996))
Category: Memory
Keyword: 
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