Dajiang ZHOU


Distortion Control and Optimization for Lossy Embedded Compression in Video Codec System
Li GUO Dajiang ZHOU Shinji KIMURA Satoshi GOTO 
Publication:   
Publication Date: 2017/11/01
Vol. E100-A  No. 11  pp. 2416-2424
Type of Manuscript:  PAPER
Category: Coding Theory
Keyword: 
lossy embedded compressionmemory-traffic-to-distortion optimizationdistortion controlframe-levelfixed data reduction ratio
 Summary | Full Text:PDF(3MB)

A 7-Die 3D Stacked 3840×2160@120 fps Motion Estimation Processor
Shuping ZHANG Jinjia ZHOU Dajiang ZHOU Shinji KIMURA Satoshi GOTO 
Publication:   
Publication Date: 2017/03/01
Vol. E100-C  No. 3  pp. 223-231
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power and High-Speed Chips)
Category: 
Keyword: 
3D IC designmotion estimation processorhamburger architecturememory stacking
 Summary | Full Text:PDF(1.6MB)

Accelerating HEVC Inter Prediction with Improved Merge Mode Handling
Zhengxue CHENG Heming SUN Dajiang ZHOU Shinji KIMURA 
Publication:   
Publication Date: 2017/02/01
Vol. E100-A  No. 2  pp. 546-554
Type of Manuscript:  Special Section PAPER (Special Section on Image Media Quality)
Category: VIDEO CODING
Keyword: 
HEVC/H.265merge modeinter predictionencoding
 Summary | Full Text:PDF(2.4MB)

A Low-Power VLSI Architecture for HEVC De-Quantization and Inverse Transform
Heming SUN Dajiang ZHOU Shuping ZHANG Shinji KIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/12/01
Vol. E99-A  No. 12  pp. 2375-2387
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
HEVCde-quantizationinverse transformlow-powerlow-costvideo coding
 Summary | Full Text:PDF(3MB)

High Performance VLSI Architecture of H.265/HEVC Intra Prediction for 8K UHDTV Video Decoder
Jianbin ZHOU Dajiang ZHOU Shihao WANG Takeshi YOSHIMURA Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/12/01
Vol. E98-A  No. 12  pp. 2519-2527
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
HEVC/H.265 decoderintra predictionVLSI architecture8K UHDTV
 Summary | Full Text:PDF(2.2MB)

Low-Power Motion Estimation Processor with 3D Stacked Memory
Shuping ZHANG Jinjia ZHOU Dajiang ZHOU Shinji KIMURA Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/07/01
Vol. E98-A  No. 7  pp. 1431-1441
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
3DIC designmotion estimation processorlow power designmemory stacking
 Summary | Full Text:PDF(4.1MB)

Unified Parameter Decoder Architecture for H.265/HEVC Motion Vector and Boundary Strength Decoding
Shihao WANG Dajiang ZHOU Jianbin ZHOU Takeshi YOSHIMURA Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/07/01
Vol. E98-A  No. 7  pp. 1356-1365
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
UHDTVH.265/HEVCparameter decodermotion vectorboundary strength
 Summary | Full Text:PDF(3.6MB)

Fast SAO Estimation Algorithm and Its Implementation for 8K×4K @ 120 FPS HEVC Encoding
Jiayi ZHU Dajiang ZHOU Shinji KIMURA Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/12/01
Vol. E97-A  No. 12  pp. 2488-2497
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
high efficiency video codingsample adaptive offsetRate Distortion Optimization (RDO) VLSI architecture
 Summary | Full Text:PDF(4.1MB)

A Low-Cost VLSI Architecture of Multiple-Size IDCT for H.265/HEVC
Heming SUN Dajiang ZHOU Peilin LIU Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/12/01
Vol. E97-A  No. 12  pp. 2467-2476
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
HEVCIDCTSRAMarea-efficientvideo coding
 Summary | Full Text:PDF(3.1MB)

Fast Prediction Unit Selection and Mode Selection for HEVC Intra Prediction
Heming SUN Dajiang ZHOU Peilin LIU Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/02/01
Vol. E97-A  No. 2  pp. 510-519
Type of Manuscript:  Special Section PAPER (Special Section on Image Media Quality)
Category: 
Keyword: 
intra predictionhigh efficiency video coding (HEVC)H.264/AVCvideo codingprediction unit size selectionmode selection
 Summary | Full Text:PDF(2.4MB)

A 5.83pJ/bit/iteration High-Parallel Performance-Aware LDPC Decoder IP Core Design for WiMAX in 65nm CMOS
Xiongxin ZHAO Zhixiang CHEN Xiao PENG Dajiang ZHOU Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/12/01
Vol. E96-A  No. 12  pp. 2623-2632
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
WiMAXbit-serialfully-parallellayered schedulingperformance awareadvanced dynamic quantizationquasi-cycliclow-density parity-check codes
 Summary | Full Text:PDF(2.2MB)

A High Performance HEVC De-Blocking Filter and SAO Architecture for UHDTV Decoder
Jiayi ZHU Dajiang ZHOU Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/12/01
Vol. E96-A  No. 12  pp. 2612-2622
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
DBFSAOHEVCpipeline
 Summary | Full Text:PDF(4MB)

A Dual-Mode Deblocking Filter Design for HEVC and H.264/AVC
Muchen LI Jinjia ZHOU Dajiang ZHOU Xiao PENG Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/06/01
Vol. E96-A  No. 6  pp. 1366-1375
Type of Manuscript:  Special Section PAPER (Special Section on Circuit, System, and Computer Technologies)
Category: 
Keyword: 
HEVCH.264/AVCdeblocking filterdual-modelow powerSHVHD
 Summary | Full Text:PDF(2.7MB)

A 115 mW 1 Gbps Bit-Serial Layered LDPC Decoder for WiMAX
Xiongxin ZHAO Xiao PENG Zhixiang CHEN Dajiang ZHOU Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A  No. 12  pp. 2384-2391
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
WiMAXbit-seriallayered schedulingQC-LDPC
 Summary | Full Text:PDF(3MB)

A 6.72-Gb/s 8 pJ/bit/iteration IEEE 802.15.3c LDPC Decoder Chip
Zhixiang CHEN Xiao PENG Xiongxin ZHAO Leona OKAMURA Dajiang ZHOU Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12  pp. 2587-2596
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
WPANIEEE802.15.3cLDPC decoderhigh data ratepower-efficient
 Summary | Full Text:PDF(1.6MB)

A 98 GMACs/W 32-Core Vector Processor in 65 nm CMOS
Xun HE Xin JIN Minghui WANG Dajiang ZHOU Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12  pp. 2609-2618
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
SIMDcache coherenceNoCGMACsmulticore processor
 Summary | Full Text:PDF(3.6MB)

A 530 Mpixels/s Intra Prediction Architecture for Ultra High Definition H.264/AVC Encoder
Gang HE Dajiang ZHOU Jinjia ZHOU Tianruo ZHANG Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/04/01
Vol. E94-C  No. 4  pp. 419-427
Type of Manuscript:  Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category: 
Keyword: 
H.264/AVCintra predictiondata dependencyhardware architecture
 Summary | Full Text:PDF(2.1MB)

Cache Based Motion Compensation Architecture for Quad-HD H.264/AVC Video Decoder
Jinjia ZHOU Dajiang ZHOU Gang HE Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/04/01
Vol. E94-C  No. 4  pp. 439-447
Type of Manuscript:  Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category: 
Keyword: 
H.264/AVCmotion compensation2-D cacheinterpolationQuad-HDultra high definition
 Summary | Full Text:PDF(1.1MB)

A Bandwidth Optimized, 64 Cycles/MB Joint Parameter Decoder Architecture for Ultra High Definition H.264/AVC Applications
Jinjia ZHOU Dajiang ZHOU Xun HE Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/08/01
Vol. E93-A  No. 8  pp. 1425-1433
Type of Manuscript:  Special Section PAPER (Special Section on Signal Processing)
Category: VLSI Design Technology and CAD
Keyword: 
motion vector derivationDRAM bandwidthultra high resolutionvideo decoderH.264/AVC
 Summary | Full Text:PDF(914.3KB)

A High Performance and Low Bandwidth Multi-Standard Motion Compensation Design for HD Video Decoder
Xianmin CHEN Peilin LIU Dajiang ZHOU Jiayi ZHU Xingguang PAN Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/03/01
Vol. E93-C  No. 3  pp. 253-260
Type of Manuscript:  Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category: 
Keyword: 
high performancelow bandwidthmotion compensationmulti-standard2-D cache
 Summary | Full Text:PDF(785.5KB)

A 48 Cycles/MB H.264/AVC Deblocking Filter Architecture for Ultra High Definition Applications
Dajiang ZHOU Jinjia ZHOU Jiayi ZHU Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12  pp. 3203-3210
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Embedded, Real-Time and Reconfigurable Systems
Keyword: 
H.264/AVCparalleldeblockingultra high resolutionQFHD
 Summary | Full Text:PDF(2.1MB)

An Efficient Motion Vector Coding Scheme Based on Prioritized Reference Decision
Dajiang ZHOU Jinjia ZHOU Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/08/01
Vol. E92-A  No. 8  pp. 1978-1985
Type of Manuscript:  Special Section PAPER (Special Section on Signal Processing)
Category: Realization
Keyword: 
video codingmotion vector codingmotion vector differencemedian predictionprioritized reference decision
 Summary | Full Text:PDF(309.8KB)