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Cong-Kha PHAM

Low Complexity Logarithmic and Anti-Logarithmic Converters for Hybrid Number System Processors and DSP Applications Van-Phuc HOANG Cong-Kha PHAM
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/02/01 Vol. E96-A No. 2 pp. 584-590 Type of Manuscript: PAPER Category: Digital Signal Processing Keyword: logarithmic converter, anti-logarithmic converter, look-up table (LUT)-based computation, digital signal processing (DSP),
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An FPGA-Based Information Detection Hardware System Employing Multi-Match Content Addressable Memory Duc-Hung LE Katsumi INOUE Masahiro SOWA Cong-Kha PHAM
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/10/01 Vol. E95-A No. 10 pp. 1708-1717 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: FPGA, information detection, content addressable memory, random access memory, parallel operation, multi-match,
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An Improved Hybrid LUT-Based Architecture for Low-Error and Efficient Fixed-Width Squarer Van-Phuc HOANG Cong-Kha PHAM
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/07/01 Vol. E95-A No. 7 pp. 1180-1184 Type of Manuscript: LETTER Category: Digital Signal Processing Keyword: lookup table (LUT)-based computation, fixed-width squarer, truncated squarer, digital signal processing (DSP),
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Efficient LUT-Based Truncated Multiplier and Its Application in RGB to YCbCr Color Space Conversion Van-Phuc HOANG Cong-Kha PHAM
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/06/01 Vol. E95-A No. 6 pp. 999-1006 Type of Manuscript: PAPER Category: Digital Signal Processing Keyword: LUT-based computation, truncated multiplier, FPGA, color space conversion,
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An Improved Linear Difference Method with High ROM Compression Ratio in Direct Digital Frequency Synthesizer Van-Phuc HOANG Cong-Kha PHAM
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/03/01 Vol. E94-A No. 3 pp. 995-998 Type of Manuscript: LETTER Category: Digital Signal Processing Keyword: DDFS, frequency synthesizer, ROM compression, difference method,
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A Low-Power High Accuracy Over Current Protection Circuit for Low Dropout Regulator Socheat HENG Cong-Kha PHAM
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2009/09/01 Vol. E92-C No. 9 pp. 1208-1214 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: over current protection, limiting current, holding current, low dropout regulator, low power, low voltage,
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Discrete Time Cellular Neural Networks with Two Types of Neuron Circuits for Image Coding and Their VLSI Implementations Cong-Kha PHAM Munemitsu IKEGAMI Mamoru TANAKA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1995/08/20 Vol. E78-A No. 8 pp. 978-988 Type of Manuscript: Special Section PAPER (Special Section on Digital Signal Processing) Category: Keyword: cellular neural network, retina, neuron circuit, nonlinear dynamics, haftoning, image coding, analog-to-digital converter,
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Chaotic Behavior in Simple Looped MOS Inverters Cong-Kha PHAM Mamoru TANAKA Katsufusa SHONO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1995/03/20 Vol. E78-A No. 3 pp. 291-299 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 7th Karuizawa Workshop on Circuits and Systems) Category: Nonlinear Problems Keyword: bifurcation, chaos, chaotic behavior, sigmoid function, inverter, transfer characteristic, nonlinear mapping function, switched capacitor (SC), CMOS switch, hold capacitor,
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A Hardware Accelerator for Design-Rule Checking in a Bit-Mapping CAD System Cong-Kha PHAM Katsufusa SHONO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1993/10/20 Vol. E76-A No. 10 pp. 1684-1693 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: design-rule, raster-based, Manhattan style, bit-mapping CAD,
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A CMOS Cell Compiler for a Bit-Mapping CAD System Cong-Kha PHAM Katsufusa SHONO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1991/09/20 Vol. E74-A No. 9 pp. 2603-2611 Type of Manuscript: PAPER Category: Computer Aided Design (CAD) Keyword:
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