Cong-Kha PHAM


A Perpetuum Mobile 32bit CPU on 65nm SOTB CMOS Technology with Reverse-Body-Bias Assisted Sleep Mode
Koichiro ISHIBASHI Nobuyuki SUGII Shiro KAMOHARA Kimiyoshi USAMI Hideharu AMANO Kazutoshi KOBAYASHI Cong-Kha PHAM 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2015/07/01
Vol. E98-C  No. 7  pp. 536-543
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power and High-Speed Chips)
Category: 
Keyword: 
microprocessorlow power design
 Summary | Full Text:PDF(2.2MB)

A CAM-Based Information Detection Hardware System for Fast Image Matching on FPGA
Duc-Hung LE Tran-Bao-Thuong CAO Katsumi INOUE Cong-Kha PHAM 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2014/01/01
Vol. E97-C  No. 1  pp. 65-76
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
FPGAInformation Detection Hardware SystemCAMdual-port RAMmulti-matchimage matching
 Summary | Full Text:PDF(4.9MB)

Design a Fast CAM-Based Exact Pattern Matching System on FPGA and 0.18µm CMOS Process
Duc-Hung LE Katsumi INOUE Cong-Kha PHAM 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/09/01
Vol. E96-A  No. 9  pp. 1883-1888
Type of Manuscript:  LETTER
Category: VLSI Design Technology and CAD
Keyword: 
FPGAASICmatching systemContent Addressable Memory (CAM)multi-matchexact pattern matching
 Summary | Full Text:PDF(651.7KB)

Low Complexity Logarithmic and Anti-Logarithmic Converters for Hybrid Number System Processors and DSP Applications
Van-Phuc HOANG Cong-Kha PHAM 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/02/01
Vol. E96-A  No. 2  pp. 584-590
Type of Manuscript:  PAPER
Category: Digital Signal Processing
Keyword: 
logarithmic converteranti-logarithmic converterlook-up table (LUT)-based computationdigital signal processing (DSP)
 Summary | Full Text:PDF(1.1MB)

An FPGA-Based Information Detection Hardware System Employing Multi-Match Content Addressable Memory
Duc-Hung LE Katsumi INOUE Masahiro SOWA Cong-Kha PHAM 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/10/01
Vol. E95-A  No. 10  pp. 1708-1717
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
FPGAinformation detectioncontent addressable memoryrandom access memoryparallel operationmulti-match
 Summary | Full Text:PDF(1MB)

An Improved Hybrid LUT-Based Architecture for Low-Error and Efficient Fixed-Width Squarer
Van-Phuc HOANG Cong-Kha PHAM 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/07/01
Vol. E95-A  No. 7  pp. 1180-1184
Type of Manuscript:  LETTER
Category: Digital Signal Processing
Keyword: 
lookup table (LUT)-based computationfixed-width squarertruncated squarerdigital signal processing (DSP)
 Summary | Full Text:PDF(658.7KB)

Efficient LUT-Based Truncated Multiplier and Its Application in RGB to YCbCr Color Space Conversion
Van-Phuc HOANG Cong-Kha PHAM 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/06/01
Vol. E95-A  No. 6  pp. 999-1006
Type of Manuscript:  PAPER
Category: Digital Signal Processing
Keyword: 
LUT-based computationtruncated multiplierFPGAcolor space conversion
 Summary | Full Text:PDF(1.2MB)

An Improved Linear Difference Method with High ROM Compression Ratio in Direct Digital Frequency Synthesizer
Van-Phuc HOANG Cong-Kha PHAM 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/03/01
Vol. E94-A  No. 3  pp. 995-998
Type of Manuscript:  LETTER
Category: Digital Signal Processing
Keyword: 
DDFSfrequency synthesizerROM compressiondifference method
 Summary | Full Text:PDF(162.3KB)

A Low-Power High Accuracy Over Current Protection Circuit for Low Dropout Regulator
Socheat HENG Cong-Kha PHAM 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/09/01
Vol. E92-C  No. 9  pp. 1208-1214
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
over current protectionlimiting currentholding currentlow dropout regulatorlow powerlow voltage
 Summary | Full Text:PDF(426.9KB)

Discrete Time Cellular Neural Networks with Two Types of Neuron Circuits for Image Coding and Their VLSI Implementations
Cong-Kha PHAM Munemitsu IKEGAMI Mamoru TANAKA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/08/25
Vol. E78-A  No. 8  pp. 978-988
Type of Manuscript:  Special Section PAPER (Special Section on Digital Signal Processing)
Category: 
Keyword: 
cellular neural networkretinaneuron circuitnonlinear dynamicshaftoningimage codinganalog-to-digital converter
 Summary | Full Text:PDF(1.3MB)

Chaotic Behavior in Simple Looped MOS Inverters
Cong-Kha PHAM Mamoru TANAKA Katsufusa SHONO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/03/25
Vol. E78-A  No. 3  pp. 291-299
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 7th Karuizawa Workshop on Circuits and Systems)
Category: Nonlinear Problems
Keyword: 
bifurcationchaoschaotic behaviorsigmoid functioninvertertransfer characteristicnonlinear mapping functionswitched capacitor (SC)CMOS switchhold capacitor
 Summary | Full Text:PDF(700.2KB)

A Hardware Accelerator for Design-Rule Checking in a Bit-Mapping CAD System
Cong-Kha PHAM Katsufusa SHONO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/10/25
Vol. E76-A  No. 10  pp. 1684-1693
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
design-ruleraster-basedManhattan stylebit-mapping CAD
 Summary | Full Text:PDF(1.1MB)

A CMOS Cell Compiler for a Bit-Mapping CAD System
Cong-Kha PHAM Katsufusa SHONO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1991/09/25
Vol. E74-A  No. 9  pp. 2603-2611
Type of Manuscript:  PAPER
Category: Computer Aided Design (CAD)
Keyword: 
 Summary | Full Text:PDF(634.7KB)