Chung-Kuan CHENG


Efficient Power Network Analysis with Modeling of Inductive Effects
Shan ZENG Wenjian YU Xianlong HONG Chung-Kuan CHENG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/06/01
Vol. E93-A  No. 6  pp. 1196-1203
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
frequency-domain analysisinductive modelingpartial reluctancepower networktime-domain voltage response
 Summary | Full Text:PDF(678.4KB)

Efficient Partial Reluctance Extraction for Large-Scale Regular Power Grid Structures
Shan ZENG Wenjian YU Jin SHI Xianlong HONG Chung-Kuan CHENG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/06/01
Vol. E92-A  No. 6  pp. 1476-1484
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
high-frequency effectinductance modelingparasitic extractionpartial reluctancepower/ground grid
 Summary | Full Text:PDF(673.6KB)

Accurate Eye Diagram Prediction Based on Step Response and Its Application to Low-Power Equalizer Design
Wenjian YU Rui SHI Chung-Kuan CHENG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/04/01
Vol. E92-C  No. 4  pp. 444-452
Type of Manuscript:  Special Section PAPER (Special Section on Low-Leakage, Low-Voltage, Low-Power and High-Speed Technologies for System LSIs in Deep-Submicron Era)
Category: 
Keyword: 
eye diagramjitterlossy transmission linestep response
 Summary | Full Text:PDF(965.2KB)

Analytical Eye-Diagram Model for On-Chip Distortionless Transmission Lines and Its Application to Design Space Exploration
Masanori HASHIMOTO Jangsombatsiri SIRIPORN Akira TSUCHIYA Haikun ZHU Chung-Kuan CHENG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12  pp. 3474-3480
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Device and Circuit Modeling and Analysis
Keyword: 
eye-diagramon-chip transmission linewaveform distortionresistive terminationshunt conductance
 Summary | Full Text:PDF(801.1KB)

VLSI Floorplanning with Boundary Constraints Using Corner Block List Representation
Yuchun MA Xianlong HONG Sheqin DONG Yici CAI Chung-Kuan CHENG Jun GU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11  pp. 2697-2704
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Layout
Keyword: 
floorplancorner block listsimulated annealingboundary constraints
 Summary | Full Text:PDF(2.1MB)