Chris MYERS


Scheduling Methods for Asynchronous Circuits with Bundled-Data Implementations Based on the Approximation of Start Times
Hiroshi SAITO Naohiro HAMADA Nattha JINDAPETCH Tomohiro YONEDA Chris MYERS Takashi NANYA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/12/01
Vol. E90-A  No. 12  pp. 2790-2799
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: System Level Design
Keyword: 
asynchronous circuitsschedulingstart timesand control steps
 Summary | Full Text:PDF(501.6KB)

Failure Trace Analysis of Timed Circuits for Automatic Timing Constraints Derivation
Tomoya KITAI Tomohiro YONEDA Chris MYERS 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/11/01
Vol. E88-D  No. 11  pp. 2555-2564
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
trace theoretic verificationfailure analysistimed circuitstiming constraints
 Summary | Full Text:PDF(815.5KB)

Partial Order Reduction for Detecting Safety and Timing Failures of Timed Circuits
Denduang PRADUBSUWUN Tomohiro YONEDA Chris MYERS 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/07/01
Vol. E88-D  No. 7  pp. 1646-1661
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
timed trace theorytimed circuitsformal verificationsafety/timing failures
 Summary | Full Text:PDF(1MB)

Partial Order Reduction for Timed Circuit Verification Based on Level Oriented Model
Tomoya KITAI Yusuke OGURO Tomohiro YONEDA Eric MERCER Chris MYERS 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/12/01
Vol. E86-D  No. 12  pp. 2601-2611
Type of Manuscript:  Special Section PAPER (Special Issue on Dependable Computing)
Category: Verification and Dependability Analysis
Keyword: 
Level-oriented modeltimed asynchronous circuitsformal verificationtime Petri nets
 Summary | Full Text:PDF(1006.1KB)

Modular Synthesis of Timed Circuits Using Partial Order Reduction
Tomohiro YONEDA Eric MERCER Chris MYERS 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A  No. 12  pp. 2684-2692
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
logic synthesispartial order reductiontimed circuitsmodular synthesis
 Summary | Full Text:PDF(568.5KB)

Framework of Timed Trace Theoretic Verification Revisited
Bin ZHOU Tomohiro YONEDA Chris MYERS 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10  pp. 1595-1604
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: Verification
Keyword: 
timed trace theorytrace structurestime Petri netsformal verificationasynchronous circuits
 Summary | Full Text:PDF(376.6KB)