IEICE SEARCH SYSTEM

Chia-Chun TSAI

Post-Routing Double-Via Insertion for X-Architecture Clock Tree Yield Improvement Chia-Chun TSAI Chung-Chieh KUO Trong-Yen LEE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/02/01 Vol. E94-A No. 2 pp. 706-716 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: clock routing, design for manufacturability, double via, X-architecture,
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GDME: Grey Relational Clustering Applied to a Clock Tree Construction with Zero Skew and Minimal Delay Chia-Chun TSAI Jan-Ou WU Trong-Yen LEE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/01/01 Vol. E91-A No. 1 pp. 365-374 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: SoC, clock tree, zero skew, grey relational clustering, DME (deferred-merge embedding), RLC delay model,
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Zero-Skew Driven Buffered RLC Clock Tree Construction Jan-Ou WU Chia-Chun TSAI Chung-Chieh KUO Trong-Yen LEE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/03/01 Vol. E90-A No. 3 pp. 651-658 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: clock tree, upward propagation, buffer insertion, zero skew, SoC,
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A New Approach to the Ball Grid Array Package Routing Shuenn-Shi CHEN Jong-Jang CHEN Trong-Yen LEE Chia-Chun TSAI Sao-Jie CHEN
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/11/20 Vol. E82-A No. 11 pp. 2599-2608 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: ball grid array (BGA), pin grid array (PGA), inversion table,
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