Bumchul KIM


High-Level Synthesis of VLSI Processors for Intelligent Integrated Systems
Yasuaki SAWANO Bumchul KIM Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/07/25
Vol. E77-C  No. 7  pp. 1101-1107
Type of Manuscript:  Special Section PAPER (Special Issue on Super Chip for Intelligent Integrated Systems)
Category: 
Keyword: 
intelligent integrated systemshigh-level synthesisparallel processingminimum latencyscheduling
 Summary | Full Text:PDF(568.6KB)

Unified Scheduling of High Performance Parallel VLSI Processors for Robotics
Bumchul KIM Michitaka KAMEYAMA Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/06/25
Vol. E76-A  No. 6  pp. 904-910
Type of Manuscript:  Special Section PAPER (Special Section on Papers Selected from 1992 Joint Technical Conference on Circuits/Systems,Computers and Communications (JTC-CSCC'92))
Category: Parallel Processor Scheduling
Keyword: 
minimum-latency architecturespecial-purpose VLSI processorparallel processingcommunication timebus interconnection network
 Summary | Full Text:PDF(514.9KB)

Parallel VLSI Processors for Robotics Using Multiple Bus Interconnection Networks
Bumchul KIM Michitaka KAMEYAMA Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/06/25
Vol. E75-A  No. 6  pp. 712-719
Type of Manuscript:  Special Section PAPER (Special Section of Papers Selected from 1991 Joint Technical Conference on Circuits/Systems, Computers and Communications (JTC-CSCC '91))
Category: Robot Electronics
Keyword: 
minimum-delay-time architectureVLSI processor for roboticsparallel processingparallel communicationmultiple bus interconnection networks
 Summary | Full Text:PDF(555.1KB)